[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Avoid redundant if condition

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38992 )

Change subject: soc/intel/icelake: Avoid redundant if condition
......................................................................

soc/intel/icelake: Avoid redundant if condition

This patch overrides "GtFreqMax" and "CdClock" FSP UPD as part of existing
IGD enable if condition check itself.

Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b
Signed-off-by: Subrata Banik 
---
M src/soc/intel/icelake/fsp_params.c
1 file changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38992/1

diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 448b82c..8efdb56 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -92,14 +92,16 @@
    mainboard_silicon_init_params(params);

dev = pcidev_path_on_root(SA_DEVFN_IGD);
-	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) {
    	params->PeiGraphicsPeimInit = 1;
-	else
-		params->PeiGraphicsPeimInit = 0;
-	if (dev && dev->enabled) {
    	params->GtFreqMax = 2;
    	params->CdClock = 3;
-	}
+	} else
+		/*
+		 * Skip IGD initialization in FSP in case device is disabled
+		 * in the devicetree.cb.
+		 */
+		params->PeiGraphicsPeimInit = 0;

/* Unlock upper 8 bytes of RTC RAM */
    params->PchLockDownRtcMemoryLock = 0;