[coreboot-gerrit] Change in coreboot[master]: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46272 )

Change subject: soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
......................................................................

soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code

Copy the AES-NI locking function to common cpu code to be able to reuse
it.

This change only copies the code and adds the MSR header file. Any
further rework and later deduplication on the platforms code is done in
the follow-up changes.

Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Nico Huber 
---
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
A src/include/cpu/intel/msr.h
3 files changed, 37 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index df14668..aaeca1d 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -27,4 +27,10 @@
  */
 bool intel_ht_sibling(void);

+/*
+ * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling
+ * as suggested in Intel document 325384-070US.
+ */
+void set_aesni_lock(void);
+
 #endif
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 3e5b578..e532c97 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -3,6 +3,7 @@
 #include <acpi/acpigen.h>
 #include <arch/cpu.h>
 #include <console/console.h>
+#include <cpu/intel/msr.h>
 #include <cpu/x86/msr.h>
 #include "common.h"

@@ -264,3 +265,22 @@
    	config->regs[CPPC_AUTO_SELECT] = msr;
    }
 }
+
+/*
+ * Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling
+ * as suggested in Intel document 325384-070US.
+ */
+void set_aesni_lock(void)
+{
+	msr_t msr;
+
+	/* Only run once per core as specified in the MSR datasheet */
+	if (intel_ht_sibling())
+		return;
+
+	msr = rdmsr(MSR_FEATURE_CONFIG);
+	if ((msr.lo & 1) == 0) {
+		msr.lo |= 1;
+		wrmsr(MSR_FEATURE_CONFIG, msr);
+	}
+}
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
new file mode 100644
index 0000000..73dd320
--- /dev/null
+++ b/src/include/cpu/intel/msr.h
@@ -0,0 +1,11 @@
+#ifndef CPU_INTEL_MSR_H
+#define CPU_INTEL_MSR_H
+
+/*
+ * Common MSRs for Intel CPUs
+ */
+
+#define MSR_FEATURE_CONFIG	0x13c
+#define  AESNI_LOCK_BIT		0
+
+#endif /* CPU_INTEL_MSR_H */