[coreboot-gerrit] Change in coreboot[master]: helios: Add TEMP_SENSOR4 to DPTF

[Shelley Chen (Code Review)]

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35920 )

Change subject: helios: Add TEMP_SENSOR4 to DPTF
......................................................................

helios: Add TEMP_SENSOR4 to DPTF

Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to
the DPTF.

BRANCH=None
BUG=b:142266102
TEST=`emerge-hatch coreboot`
Verify that Helios builds correctly.

Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a
Signed-off-by: Paul Fagerburg 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920
Tested-by: build bot (Jenkins) 
Reviewed-by: Shelley Chen 
---
M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
1 file changed, 18 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Shelley Chen: Looks good to me, approved

diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
index e3159c8..0013f29 100644
--- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl
@@ -54,6 +54,17 @@
 #define DPTF_TSR2_ACTIVE_AC4	40
 #define DPTF_TSR2_ACTIVE_AC5	38

+#define DPTF_TSR3_SENSOR_ID	3
+#define DPTF_TSR3_SENSOR_NAME	"CPU"
+#define DPTF_TSR3_PASSIVE	85
+#define DPTF_TSR3_CRITICAL	100
+#define DPTF_TSR3_ACTIVE_AC0	0
+#define DPTF_TSR3_ACTIVE_AC1	0
+#define DPTF_TSR3_ACTIVE_AC2	0
+#define DPTF_TSR3_ACTIVE_AC3	0
+#define DPTF_TSR3_ACTIVE_AC4	0
+#define DPTF_TSR3_ACTIVE_AC5	0
+
 #define DPTF_ENABLE_CHARGER
 #define DPTF_ENABLE_FAN_CONTROL

@@ -107,6 +118,10 @@
    Package () {
    	_SB.DPTF.TFN1, _SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 30, 0,
    		0, 0, 0
+	},
+	Package () {
+		_SB.DPTF.TFN1, _SB.DPTF.TSR3, 100, 90, 69, 56, 46, 36, 30, 0,
+			0, 0, 0
    }
 })

@@ -122,6 +137,9 @@

/* CPU Throttle Effect on TSR2 */
    Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on TSR3 */
+	Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
 })

Name (MPPC, Package ()