Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37211 )
Change subject: [WIP] soc/amd/common: Inline ACPI MMIO accessors ......................................................................
[WIP] soc/amd/common: Inline ACPI MMIO accessors
TBD: Verify better code density from assembly.
Change-Id: If2c37c9886a0151183aa6dd80eb068d6c67b3848 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 321 insertions(+), 433 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37211/1
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index f844ea4..7a4e606 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -14,8 +14,6 @@ */
#include <types.h> -#include <arch/io.h> -#include <device/mmio.h> #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h>
@@ -27,337 +25,3 @@ dw |= ACPIMMIO_DECODE_EN; pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw); } - -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); -} - -uint32_t pm_io_read32(uint8_t reg) -{ - return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - pm_io_write8(reg, value & 0xff); - value >>= 8; - pm_io_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - pm_io_write16(reg, value & 0xffff); - value >>= 16; - pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); -} - -/* smbus pci read/write - access registers at 0xfed80000 */ - -u8 sm_pci_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -u16 sm_pci_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -u32 sm_pci_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); -} - -void sm_pci_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -void sm_pci_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -void sm_pci_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); -} - -uint8_t smi_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -uint16_t smi_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -uint32_t smi_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_SMI_BASE + reg)); -} - -void smi_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -void smi_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -void smi_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_SMI_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); -} - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - -uint8_t biosram_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); -} - -uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ -{ - return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); -} - -uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - -void biosram_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); -} - -void biosram_write16(uint8_t reg, uint16_t value) -{ - biosram_write8(reg, value & 0xff); - value >>= 8; - biosram_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void biosram_write32(uint8_t reg, uint32_t value) -{ - biosram_write16(reg, value & 0xffff); - value >>= 16; - biosram_write16(reg + sizeof(uint16_t), value & 0xffff); -} - -u8 acpi_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); -} - -u8 asf_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -u16 asf_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); -} - -void asf_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -void asf_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); -} - -u8 smbus_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -u16 smbus_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); -} - -void smbus_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -void smbus_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); -} - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); -} - -u8 misc_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); -} - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); -} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b395cdb..53d1f043 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,7 +18,11 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__
+#include <arch/io.h> +#include <device/mmio.h> #include <stdint.h> +#include <types.h> +#include <amdblocks/acpimmio_map.h>
/* * The following AcpiMmio register block mapping represents definitions @@ -100,116 +104,336 @@ /* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void);
-/* Access SMBus PCI registers at 0xfed80000 */ -uint8_t sm_pci_read8(uint8_t reg); -uint16_t sm_pci_read16(uint8_t reg); -uint32_t sm_pci_read32(uint8_t reg); -void sm_pci_write8(uint8_t reg, uint8_t value); -void sm_pci_write16(uint8_t reg, uint16_t value); -void sm_pci_write32(uint8_t reg, uint32_t value); +/* PM registers are accessed a byte at a time via CD6/CD7 */ +static inline uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +}
-/* Access PM registers using IO cycles */ -uint8_t pm_io_read8(uint8_t reg); -uint16_t pm_io_read16(uint8_t reg); -uint32_t pm_io_read32(uint8_t reg); -void pm_io_write8(uint8_t reg, uint8_t value); -void pm_io_write16(uint8_t reg, uint16_t value); -void pm_io_write32(uint8_t reg, uint32_t value); +static inline uint16_t pm_io_read16(uint8_t reg) +{ + return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); +}
-/* Access SMI registers at 0xfed80100 */ -uint8_t smi_read8(uint8_t reg); -uint16_t smi_read16(uint8_t reg); -uint32_t smi_read32(uint8_t reg); -void smi_write8(uint8_t reg, uint8_t value); -void smi_write16(uint8_t reg, uint16_t value); -void smi_write32(uint8_t reg, uint32_t value); +static inline uint32_t pm_io_read32(uint8_t reg) +{ + return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); +}
-/* Access Power Management registers at 0xfed80300 */ -uint8_t pm_read8(uint8_t reg); -uint16_t pm_read16(uint8_t reg); -uint32_t pm_read32(uint8_t reg); -void pm_write8(uint8_t reg, uint8_t value); -void pm_write16(uint8_t reg, uint16_t value); -void pm_write32(uint8_t reg, uint32_t value); +static inline void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +}
-/* Access Power Management 2 registers at 0xfed80400 */ -uint8_t pm2_read8(uint8_t reg); -uint16_t pm2_read16(uint8_t reg); -uint32_t pm2_read32(uint8_t reg); -void pm2_write8(uint8_t reg, uint8_t value); -void pm2_write16(uint8_t reg, uint16_t value); -void pm2_write32(uint8_t reg, uint32_t value); +static inline void pm_io_write16(uint8_t reg, uint16_t value) +{ + pm_io_write8(reg, value & 0xff); + value >>= 8; + pm_io_write8(reg + sizeof(uint8_t), value & 0xff); +}
-/* Access BIOS RAM storage at 0xfed80500 */ -uint8_t biosram_read8(uint8_t reg); -uint16_t biosram_read16(uint8_t reg); -uint32_t biosram_read32(uint8_t reg); -void biosram_write8(uint8_t reg, uint8_t value); -void biosram_write16(uint8_t reg, uint16_t value); -void biosram_write32(uint8_t reg, uint32_t value); +static inline void pm_io_write32(uint8_t reg, uint32_t value) +{ + pm_io_write16(reg, value & 0xffff); + value >>= 16; + pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); +}
-/* Access ACPI registers at 0xfed80800 */ -uint8_t acpi_read8(uint8_t reg); -uint16_t acpi_read16(uint8_t reg); -uint32_t acpi_read32(uint8_t reg); -void acpi_write8(uint8_t reg, uint8_t value); -void acpi_write16(uint8_t reg, uint16_t value); -void acpi_write32(uint8_t reg, uint32_t value); +static inline uint8_t sm_pci_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +}
-/* Access ASF controller registers at 0xfed80900 */ -uint8_t asf_read8(uint8_t reg); -uint16_t asf_read16(uint8_t reg); -void asf_write8(uint8_t reg, uint8_t value); -void asf_write16(uint8_t reg, uint16_t value); +static inline uint16_t sm_pci_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +}
-/* Access SMBus controller registers at 0xfed80a00 */ -uint8_t smbus_read8(uint8_t reg); -uint16_t smbus_read16(uint8_t reg); -void smbus_write8(uint8_t reg, uint8_t value); -void smbus_write16(uint8_t reg, uint16_t value); +static inline uint32_t sm_pci_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +}
-/* Access WDT registers at 0xfed80b00 */ -uint8_t wdt_read8(uint8_t reg); -uint16_t wdt_read16(uint8_t reg); -uint32_t wdt_read32(uint8_t reg); -void wdt_write8(uint8_t reg, uint8_t value); -void wdt_write16(uint8_t reg, uint16_t value); -void wdt_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +}
-/* Access HPET registers at 0xfed80c00 */ -uint8_t hpet_read8(uint8_t reg); -uint16_t hpet_read16(uint8_t reg); -uint32_t hpet_read32(uint8_t reg); -void hpet_write8(uint8_t reg, uint8_t value); -void hpet_write16(uint8_t reg, uint16_t value); -void hpet_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +}
-/* Access GPIO MUX registers at 0xfed80d00 */ -uint8_t iomux_read8(uint8_t reg); -uint16_t iomux_read16(uint8_t reg); -uint32_t iomux_read32(uint8_t reg); -void iomux_write8(uint8_t reg, uint8_t value); -void iomux_write16(uint8_t reg, uint16_t value); -void iomux_write32(uint8_t reg, uint32_t value); +static inline void sm_pci_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +}
-/* Access Miscellaneous registers at 0xfed80e00 */ -uint8_t misc_read8(uint8_t reg); -uint16_t misc_read16(uint8_t reg); -uint32_t misc_read32(uint8_t reg); -void misc_write8(uint8_t reg, uint8_t value); -void misc_write16(uint8_t reg, uint16_t value); -void misc_write32(uint8_t reg, uint32_t value); +static inline uint8_t smi_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SMI_BASE + reg)); +}
-/* Access xHCI Power Management registers at 0xfed81c00 */ -uint8_t xhci_pm_read8(uint8_t reg); -uint16_t xhci_pm_read16(uint8_t reg); -uint32_t xhci_pm_read32(uint8_t reg); -void xhci_pm_write8(uint8_t reg, uint8_t value); -void xhci_pm_write16(uint8_t reg, uint16_t value); -void xhci_pm_write32(uint8_t reg, uint32_t value); +static inline uint16_t smi_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + reg)); +}
-/* Access Always On Always Connect registers at 0xfed81e00 */ -uint8_t aoac_read8(uint8_t reg); -void aoac_write8(uint8_t reg, uint8_t value); +static inline uint32_t smi_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + reg)); +} + +static inline void smi_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline void smi_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline void smi_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + reg), value); +} + +static inline uint8_t pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline uint16_t pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline uint32_t pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +static inline void pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline void pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline void pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +static inline uint8_t biosram_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); +} + +static inline uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ +{ + return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); +} + +static inline uint32_t biosram_read32(uint8_t reg) +{ + uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; + return value | biosram_read16(reg); +} + +static inline void biosram_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); +} + +static inline void biosram_write16(uint8_t reg, uint16_t value) +{ + biosram_write8(reg, value & 0xff); + value >>= 8; + biosram_write8(reg + sizeof(uint8_t), value & 0xff); +} + +static inline void biosram_write32(uint8_t reg, uint32_t value) +{ + biosram_write16(reg, value & 0xffff); + value >>= 16; + biosram_write16(reg + sizeof(uint16_t), value & 0xffff); +} + +static inline uint8_t acpi_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline uint16_t acpi_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline uint32_t acpi_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +static inline void acpi_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline void acpi_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline void acpi_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +static inline uint8_t asf_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +static inline uint16_t asf_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +static inline void asf_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +static inline void asf_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +static inline uint8_t smbus_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +static inline uint16_t smbus_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +static inline void smbus_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +static inline void smbus_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +static inline uint8_t iomux_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline uint16_t iomux_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline uint32_t iomux_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +static inline void iomux_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline void iomux_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline void iomux_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +static inline uint8_t misc_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline uint16_t misc_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline uint32_t misc_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +static inline void misc_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline void misc_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline void misc_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +static inline uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +static inline void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +static inline uint8_t aoac_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +static inline void aoac_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +}
#endif /* __AMDBLOCKS_ACPIMMIO_H__ */