[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/gpio_defs: Add macros for bidirectional pad

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42914?usp=email )

(

16 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/common/gpio_defs: Add macros for bidirectional pad
......................................................................

soc/intel/common/gpio_defs: Add macros for bidirectional pad

Adds new macros to configure the pad in bidirectional mode when both
(Tx/Rx) buffers are enabled in the configuration register DW0. This
corresponds to FSP's < GpioDirInOut > parameter for port direction
(for example see config for SOUTH_GROUP0_DFX_SPARE2 pad in
src/mainboard/intel/harcuvar/gpio.h).

This macro is used in the pad configuration for some boards:
 CB:43456 - mb/intel/cedarisland_crb;
 CB:39133 - mb/kontron/mal10;
 CB:43410 - mb/51nb/x210;
 CB:43411 - mb/razer/blade_stealth_kbl.

Change-Id: I7b65f4da7616f2eefcd33a728d4d3ae5a79b014e
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42914
Reviewed-by: coreboot org 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/include/intelblocks/gpio_defs.h
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  coreboot org: Looks good to me, approved

diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
index a51ebf3..f0ff08c 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h
@@ -395,6 +395,20 @@
 #define PAD_CFG_GPI_INT_LOCK_SWAPPED(pad, pull, trig, lock_action)	\
    	PAD_CFG_GPI_TRIG_OWN_LOCK_SWAPPED(pad, pull, PWROK, trig, DRIVER, lock_action)

+/* Bidirectional GPIO port when both RX and TX buffer is enabled */
+#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |	\
+		PAD_BUF(NO_DISABLE) | val,				\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) |		\
+		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
+
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)		\
+	_PAD_CFG_STRUCT(pad,						\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |	\
+		PAD_BUF(NO_DISABLE) | val,				\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+
 /*
  * No Connect configuration for unconnected or unused pad.
  * Both TX and RX are disabled. RX disabling is done to avoid unnecessary