[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: populate some FSP-M UPDs

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 )

Change subject: soc/amd/cezanne: populate some FSP-M UPDs
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Patch Set 2:

(1 comment)

File src/soc/amd/cezanne/romstage.c:

https://review.coreboot.org/c/coreboot/+/50239/comment/4cd64a9b_e874ba31 
PS2, Line 19: 1
> Is this to handle the case of legacy IO?

no. in the mmio case the spacing between the registers might be either 1 or 4 bytes. see src/drivers/uart/uart8250mem.c