[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell/smbus.c: Add support for i2c mode block write

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33225 )

Change subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write
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Patch Set 9:
> Patch Set 9:
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> (1 comment)
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> my goal is having SMBus i2c support merged in coreboot, but I get comments which points to different ways.
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> To avoid accessing smbus registers before 'checking ready' I suggest creating do_i2c_block_write() in SB/intel/common.

I agree, you can still pass just the array of bytes to send (with count) as arguments, drop the separate offset, thus making a clean API. You can then write both CMD and DAT1 in the new implementation with sufficient commentary.

BTW: Was it actually documented for Braswell like that, such that both registers have to be written, or was this trial-and-error? Really sounds like errata to me.