Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27037
Change subject: src: Use {pci,pnp}_devfn_t instead of device_t ......................................................................
src: Use {pci,pnp}_devfn_t instead of device_t
Change-Id: I7a1a496a39b41cdf963a2e9b0042c206da52285b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/intel/apollolake/uart.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/spi.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c 15 files changed, 76 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/27037/1
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 54b280d..a59b567 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -60,7 +60,11 @@ void pch_uart_init(void) { uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS; - device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); +#else + struct device *uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); +#endif
/* Get a 0-based pad index. See invalid_uart_for_console() above. */ const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 1ea7cc2..abc4a47 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -48,7 +48,11 @@ { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev; +#else + struct device *dev; +#endif
/* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 0b8a970..24f6a3d 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -80,7 +80,11 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(bus, slot, func); +#else + struct device *dev = PCI_DEV(bus, slot, func); +#endif
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 7a764f1..7d862f2 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -266,7 +266,11 @@ uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_LPC; +#else + struct device *dev = PCH_DEV_LPC; +#endif ich9_spi_regs *ich9_spi;
pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 69a921f..d399d1b 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -140,8 +140,11 @@ pch_interrupt_routing[7] = config->pirqh_routing;
itss_irq_init(pch_interrupt_routing); - - device_t irq_dev; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t irq_dev; +#else + struct device *irq_dev; +#endif for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0;
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 6aad685..8040410 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -35,7 +35,11 @@
static const struct port { struct pad_config pads[2]; /* just TX and RX */ - device_t dev; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev; +#else + struct device *dev; +#endif } uart_ports[] = { {.dev = PCH_DEV_UART0, .pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */ diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index d8ac2f3..b49f2a3 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -134,7 +134,11 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(bus, slot, func); +#else + struct device *dev = PCI_DEV(bus, slot, func); +#endif
if (!smihandler_soc_disable_busmaster(dev)) continue; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 9af42ee..7d97661 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -31,8 +31,11 @@ u32 mmio_base) { register uint16_t reg16; - - device_t uart_dev = PCI_DEV(bus, dev, func); +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t uart_dev = PCI_DEV(bus, dev, func); +#else + struct device *uart_dev = PCI_DEV(bus, dev, func); +#endif
/* We're using MMIO for HSUARTs. This section is needed for logging * from FSP only diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 3fe41d2..813d5c6 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -30,8 +30,11 @@ /* Returns base of requested region encoded in the system agent. */ static inline uintptr_t system_agent_region_base(size_t reg) { - device_t dev = SA_DEV_ROOT; - +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = SA_DEV_ROOT; +#else + struct device *dev = SA_DEV_ROOT; +#endif /* All regions concerned for have 1 MiB alignment. */ return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB); } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 105298e..3da349a 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -50,7 +50,11 @@ static void early_pmc_init(void) { /* PMC (B0:D31:F2). */ - device_t dev = PCH_PMC_DEV; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_PMC_DEV; +#else + struct device *dev = PCH_PMC_DEV; +#endif
/* Is PMC present */ if (pci_read_config16(dev, 0) == 0xffff) { @@ -99,7 +103,11 @@ static void early_tco_init(void) { /* SMBUS (B0:D31:F4). */ - device_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); +#else + struct device *dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); +#endif
/* Configure TCO base address */ if (pci_read_config16(dev, TCOBASE) == 0xffff) { diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index e434c1c..d97bc24 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -65,7 +65,11 @@ for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(bus, slot, func); +#else + struct device *dev = PCI_DEV(bus, slot, func); +#endif
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 521a1b7..ef61a60 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -46,7 +46,7 @@
static void enable_p2sbbar(void) { - device_t dev = PCH_DEV_P2SB; + pci_devfn_t dev = PCH_DEV_P2SB;
/* Enable PCR Base address in PCH */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 7473c57..8fd6599 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -104,12 +104,12 @@ { PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, "Kabylake DT GT2" }, };
-static uint8_t get_dev_revision(device_t dev) +static uint8_t get_dev_revision(pci_devfn_t dev) { return pci_read_config8(dev, PCI_REVISION_ID); }
-static uint16_t get_dev_id(device_t dev) +static uint16_t get_dev_id(pci_devfn_t dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } @@ -171,7 +171,7 @@ static void report_mch_info(void) { int i; - device_t dev = SA_DEV_ROOT; + pci_devfn_t dev = SA_DEV_ROOT; uint16_t mchid = get_dev_id(dev); uint8_t mch_revision = get_dev_revision(dev); const char *mch_type = "Unknown"; @@ -190,7 +190,7 @@ static void report_pch_info(void) { int i; - device_t dev = PCH_DEV_LPC; + pci_devfn_t dev = PCH_DEV_LPC; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown";
@@ -207,7 +207,7 @@ static void report_igd_info(void) { int i; - device_t dev = SA_DEV_IGD; + pci_devfn_t dev = SA_DEV_IGD; uint16_t igdid = get_dev_id(dev); const char *igd_type = "Unknown";
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ecdc6bb..a2623d9 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -31,7 +31,11 @@ { /* Set the DISB after DRAM init */ u32 disb_val; - device_t dev = PCH_DEV_PMC; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_PMC; +#else + struct device *dev = PCH_DEV_PMC; +#endif
disb_val = pci_read_config32(dev, GEN_PMCON_A); disb_val |= DISB; diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index d05c812..a3974e0 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -19,8 +19,6 @@ * and the differences between PCH variants. */
-#define __SIMPLE_DEVICE__ - #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> @@ -232,7 +230,11 @@ u8 reg8; int rtc_failed; /* PMC Controller Device 0x1F, Func 02 */ - device_t dev = PCH_DEV_PMC; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCH_DEV_PMC; +#else + struct device *dev = PCH_PMC; +#endif reg8 = pci_read_config8(dev, GEN_PMCON_B); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) {