[coreboot-gerrit] [XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

[Jason-jh Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu.

Jason-jh Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email )

Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
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Patch Set 4:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86027/comment/d4ff1c94_d2ca6711?usp... :
PS3, Line 12: request
> requests

Done

https://review.coreboot.org/c/coreboot/+/86027/comment/5a3c0240_f6367a76?usp... :
PS3, Line 14: Otherwise, GCE will hang when accessing DRAM.
> Move the first few words to the previous line

Done

File src/soc/mediatek/mt8196/mminfra.c:

https://review.coreboot.org/c/coreboot/+/86027/comment/b59b6eac_cbdd9a37?usp... :
PS3, Line 35: 0x1
> Maybe just `1` for consistency?

But other places in this file also use Hex for the non-zreo settings.
So I think `0x1` should be consistent in this file.