build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26991 )
Change subject: src: Remove unneeded whitespace ......................................................................
Patch Set 3:
(23 comments)
https://review.coreboot.org/#/c/26991/3/src/include/bootstate.h File src/include/bootstate.h:
https://review.coreboot.org/#/c/26991/3/src/include/bootstate.h@127 PS3, Line 127: #define INIT_BOOT_STATE_CALLBACK_DEBUG(bscb_) \ Single statement macros should not use a do {} while (0) loop
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/agesa/family14/c... File src/northbridge/amd/agesa/family14/chip.h:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/agesa/family14/c... PS3, Line 30: * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused) line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdht/h3gtopo.h File src/northbridge/amd/amdht/h3gtopo.h:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdht/h3gtopo.h@... PS3, Line 259: 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6 line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/amddefs.h File src/northbridge/amd/amdmct/amddefs.h:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/amddefs.h... PS3, Line 77: #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) please, no space before tabs
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mct_d... File src/northbridge/amd/amdmct/mct/mct_d.c:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mct_d... PS3, Line 3756: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mctdq... File src/northbridge/amd/amdmct/mct/mctdqs_d.c:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct/mctdq... PS3, Line 464: BanksPresent = 1; /* flag for at least one bank is present */ line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... PS3, Line 7912: * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... PS3, Line 118: OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */ line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... PS3, Line 123: /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */ line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/amdmct/mct_ddr3/... PS3, Line 699: // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]); line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/lx/northbridgein... File src/northbridge/amd/lx/northbridgeinit.c:
https://review.coreboot.org/#/c/26991/3/src/northbridge/amd/lx/northbridgein... PS3, Line 597: * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late.... File src/southbridge/amd/cimx/sb800/late.c:
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late.... PS3, Line 355: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late.... PS3, Line 361: sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late.... PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb800/late.... PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late.... File src/southbridge/amd/cimx/sb900/late.c:
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late.... PS3, Line 383: sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late.... PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { Comparisons should place the constant on the right side of the test
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/cimx/sb900/late.... PS3, Line 390: if (AZALIA_DISABLE == sb_config->AzaliaController) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c:
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/gfx.c@452 PS3, Line 452: vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/rs780.c File src/southbridge/amd/rs780/rs780.c:
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/rs780/rs780.c@96 PS3, Line 96: /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ line over 80 characters
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/sr5650/cmn.h File src/southbridge/amd/sr5650/cmn.h:
https://review.coreboot.org/#/c/26991/3/src/southbridge/amd/sr5650/cmn.h@23 PS3, Line 23: #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ line over 80 characters
https://review.coreboot.org/#/c/26991/3/util/vgabios/device.c File util/vgabios/device.c:
https://review.coreboot.org/#/c/26991/3/util/vgabios/device.c@83 PS3, Line 83: DEBUG_PRINTF("%s: VGA device found, adding legacy resources...\n", __func__); line over 80 characters
https://review.coreboot.org/#/c/26991/3/util/vgabios/testbios.c File util/vgabios/testbios.c:
https://review.coreboot.org/#/c/26991/3/util/vgabios/testbios.c@119 PS3, Line 119: ("Usage: %s [-c codesegment] [-s size] [-b base] [-i ip] [-t] <filename> ...\n", line over 80 characters