Enrico Granata has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31278 )
Change subject: mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQ ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31278/1/src/ec/google/chromeec/acpi/cros_ec.... File src/ec/google/chromeec/acpi/cros_ec.asl:
https://review.coreboot.org/#/c/31278/1/src/ec/google/chromeec/acpi/cros_ec.... PS1, Line 38: GpioInt
I'm not actually quire sure how all the plumbing works, but I think we could skip the GPIO controlle […]
Sorry, I should have been more explicit. We do definitely want a direct GPIO line, not an SCI (SCI is what we were using before this change, and it doesn't have good enough latency/jitter properties for this use case).
I was just hoping there would be a way to express this interrupt in ACPI by using an Interrupt resource - because on the kernel side, using a GpioInt requires different API calls (and it's not entirely obvious how to go about "fixing" that).
I wouldn't block this CL on that though, by all means if GpioInt it needs to be, it should be a GpioInt and we will make the kernel work one way or the other.