[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brya/var/anraggar: Enable ILITEK touchscreen

[Weimin Wu (Code Review)]

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik.

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79164?usp=email )

Change subject: mb/google/brya/var/anraggar: Enable ILITEK touchscreen
......................................................................

mb/google/brya/var/anraggar: Enable ILITEK touchscreen

Fix GPP_C6 configration for ILITEK touchscreen.

BUG=b:304920262
TEST=touchscreen function works

Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d
Signed-off-by: wuweimin 
---
M src/mainboard/google/brya/variants/anraggar/gpio.c
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
2 files changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79164/1

diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c
index 686ae8b..925a622 100644
--- a/src/mainboard/google/brya/variants/anraggar/gpio.c
+++ b/src/mainboard/google/brya/variants/anraggar/gpio.c
@@ -29,6 +29,9 @@
    /* B11 : NC ==> EN_PP3300_WLAN_X*/
    PAD_CFG_GPO(GPP_B11, 0, DEEP),

+	/* GPP_C6 : NC ==> TCHSCR_REPORT_EN */
+	PAD_CFG_GPO(GPP_C6, 1, DEEP),
+
    /* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL ==> NC */
    PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
    /* D13 : NC ==> EN_PP1800_WCAM_X */
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 9c6492d..6ba43c3 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -223,8 +223,6 @@
    			register "generic.reset_delay_ms" = "200"
    			register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
    			register "generic.enable_delay_ms" = "12"
-				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
-				register "generic.stop_off_delay_ms" = "2"
    			register "generic.has_power_resource" = "1"
    			register "hid_desc_reg_offset" = "0x01"
    			device i2c 41 on end