Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 7:
(18 comments)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 23: _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0
this does not match the prior version (GPO) but now means PAD_NC. […]
PAD_NC(GPP_A12, NONE),
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 30: PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI),
changed from DRIVER to ACPI; please provide raw inteltool output
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 40: _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), : _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0
TX_RX_DISABLE + no NFx -> PAD_NC was right
yes, B2-B10 are NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 77: _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), : _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
not sure about these, yet; provide intel raw output, please
all three NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 94: G_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(
the prior version is correct
PAD_CFG_GPI_SMI(GPP_C22, 20K_PU, DEEP, EDGE_SINGLE, NONE)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 97: PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE),
TX_RX_DISABLE + no NFx -> PAD_NC was right
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 101: _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), :
TX_RX_DISABLE + no NFx -> PAD_NC was right
D0 - NC D1 is right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 104: _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K_PU
the prior version was right
PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE)
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 126: TRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 <
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 131: PAD_NC(GPP_E0, NONE),
why did this change from NF1 to NC?
NC is right
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 137: RUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) : | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(20K
the prior version was right
PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE),
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 157: G_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1),
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 173: FG_STRUCT(GPP_G0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), : _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1
probably PAD_CFG_GPI or even NC; provide raw value, please
G0-G3 NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 189: PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), : PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI
changed from DRIVER to ACPI; reason?
G12-G16 - NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 202: _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 206: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) : | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1)
probably PAD_CFG_GPI or even NC; provide raw value, please
NC
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 236: _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_TRIG(OFF) : | PAD_BUF(TX_RX_DISABLE) | 1, 0), :
TX_RX_DISABLE + no NFx -> PAD_NC was right
PAD_NC(GPD7, NONE) GPD8 is right
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
sorry for letting you wait; I'm going to check this now :)
see comments in patchset 4