Skoll RC has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40813 )
Change subject: adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details ......................................................................
adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details
Signed-off-by: Robin CASSET amisbievre@posteo.net Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c --- A src/mainboard/ongy/Kconfig A src/mainboard/ongy/Kconfig.name A src/mainboard/ongy/h61m-s1/Kconfig A src/mainboard/ongy/h61m-s1/Kconfig.name A src/mainboard/ongy/h61m-s1/Makefile.inc A src/mainboard/ongy/h61m-s1/acpi/ec.asl A src/mainboard/ongy/h61m-s1/acpi/platform.asl A src/mainboard/ongy/h61m-s1/acpi/superio.asl A src/mainboard/ongy/h61m-s1/acpi_tables.c A src/mainboard/ongy/h61m-s1/board_info.txt A src/mainboard/ongy/h61m-s1/devicetree.cb A src/mainboard/ongy/h61m-s1/dsdt.asl A src/mainboard/ongy/h61m-s1/early_init.c A src/mainboard/ongy/h61m-s1/gma-mainboard.ads A src/mainboard/ongy/h61m-s1/gpio.c A src/mainboard/ongy/h61m-s1/hda_verb.c A src/mainboard/ongy/h61m-s1/mainboard.c 17 files changed, 559 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/40813/1
diff --git a/src/mainboard/ongy/Kconfig b/src/mainboard/ongy/Kconfig new file mode 100644 index 0000000..30ea9f3 --- /dev/null +++ b/src/mainboard/ongy/Kconfig @@ -0,0 +1,14 @@ +if VENDOR_ONGY +choice + prompt "Mainboard model" + +source "src/mainboard/ongy/*/Kconfig.name" + +endchoice + +source "src/mainboard/ongy/*/Kconfig" + +config MAINBOARD_VENDOR + default "H61M-S1" + +endif # VENDOR_ONGY diff --git a/src/mainboard/ongy/Kconfig.name b/src/mainboard/ongy/Kconfig.name new file mode 100644 index 0000000..d0e84b5 --- /dev/null +++ b/src/mainboard/ongy/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ONGY + bool "ongy" diff --git a/src/mainboard/ongy/h61m-s1/Kconfig b/src/mainboard/ongy/h61m-s1/Kconfig new file mode 100644 index 0000000..65bda16 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_H61M_S1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default ongy/h61m-s1 + +config MAINBOARD_PART_NUMBER + string + default "h61m-s1" + +config VGA_BIOS_FILE + string + default "pci8086,0112.rom" + +config VGA_BIOS_ID + string + default "8086,0112" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/ongy/h61m-s1/Kconfig.name b/src/mainboard/ongy/h61m-s1/Kconfig.name new file mode 100644 index 0000000..36eed8c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_H61M_S1 + bool "h61m-s1" diff --git a/src/mainboard/ongy/h61m-s1/Makefile.inc b/src/mainboard/ongy/h61m-s1/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/ongy/h61m-s1/acpi/ec.asl b/src/mainboard/ongy/h61m-s1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/ec.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi/platform.asl b/src/mainboard/ongy/h61m-s1/acpi/platform.asl new file mode 100644 index 0000000..ac9ff88 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* The _PTS method (Prepare To Sleep) is called before the OS is +* entering a sleep state. The sleep state number is passed in Arg0 +*/ + +Method(_PTS,1) +{ +} + +/*The _WAK method is called on system wakeup*/ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ongy/h61m-s1/acpi/superio.asl b/src/mainboard/ongy/h61m-s1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/superio.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi_tables.c b/src/mainboard/ongy/h61m-s1/acpi_tables.c new file mode 100644 index 0000000..3319c25 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi_tables.c @@ -0,0 +1,22 @@ +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/ongy/h61m-s1/board_info.txt b/src/mainboard/ongy/h61m-s1/board_info.txt new file mode 100644 index 0000000..0fc073c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: none +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/ongy/h61m-s1/devicetree.cb b/src/mainboard/ongy/h61m-s1/devicetree.cb new file mode 100644 index 0000000..38b740f --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/devicetree.cb @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x1c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x1c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x1c10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x8086 0x1c1a + end + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x1c26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x8086 0x1c5c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x1c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x1c22 + end + device pci 1f.5 off end # SATA Controller 2 + + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x8086 0x0100 + end + device pci 01.0 on # PEG + subsystemid 0x8086 0x0101 + end + device pci 02.0 on # iGPU + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/ongy/h61m-s1/dsdt.asl b/src/mainboard/ongy/h61m-s1/dsdt.asl new file mode 100644 index 0000000..8c67659 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/dsdt.asl @@ -0,0 +1,43 @@ +/* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include "acpi/thermal.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/ongy/h61m-s1/early_init.c b/src/mainboard/ongy/h61m-s1/early_init.c new file mode 100644 index 0000000..6cb36f1 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/early_init.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1401); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/ongy/h61m-s1/gma-mainboard.ads b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads new file mode 100644 index 0000000..e2c84c6 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-only +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/ongy/h61m-s1/gpio.c b/src/mainboard/ongy/h61m-s1/gpio.c new file mode 100644 index 0000000..22f4838 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gpio.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/ongy/h61m-s1/hda_verb.c b/src/mainboard/ongy/h61m-s1/hda_verb.c new file mode 100644 index 0000000..09748c0 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/hda_verb.c @@ -0,0 +1,43 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek*/ + 0x10ec0000, /* Subsystem ID*/ + 12, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(2, 0x10ec0000), + AZALIA_PIN_CFG(2, 0x12, 0x40130000), + AZALIA_PIN_CFG(2, 0x14, 0x01014010), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19040), + AZALIA_PIN_CFG(2, 0x19, 0x02a19050), + AZALIA_PIN_CFG(2, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214020), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4044c601), + AZALIA_PIN_CFG(2, 0x1e, 0x01441130), + + 0x80862805, /* Codec Vendor / Device ID: Intel*/ + 0x80860101, /* Subsystem ID*/ + 4, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/ongy/h61m-s1/mainboard.c b/src/mainboard/ongy/h61m-s1/mainboard.c new file mode 100644 index 0000000..3f9c24e --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};