[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Rename `read_training` function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47576 )

Change subject: nb/intel/sandybridge: Rename `read_training` function
......................................................................

nb/intel/sandybridge: Rename `read_training` function

Given that it sets the receive enable mode bit in the GDCRTRAININGMOD
register, it's clear that this is about receive enable calibration.

Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_native.c
3 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47576/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index f20181e..9da5a97 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1307,7 +1307,7 @@
  * Once the controller has detected this pattern a bit in the result register is set for the
  * current phase shift.
  */
-int read_training(ramctr_timing *ctrl)
+int receive_enable_calibration(ramctr_timing *ctrl)
 {
    int channel, slotrank, lane;
    int err;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index de74af5..5227536 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -400,7 +400,7 @@
 void dram_zones(ramctr_timing *ctrl, int training);
 void dram_memorymap(ramctr_timing *ctrl, int me_uma_size);
 void dram_jedecreset(ramctr_timing *ctrl);
-int read_training(ramctr_timing *ctrl);
+int receive_enable_calibration(ramctr_timing *ctrl);
 int write_training(ramctr_timing *ctrl);
 int command_training(ramctr_timing *ctrl);
 int discover_edges(ramctr_timing *ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 53017eb..20009cb 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -680,7 +680,7 @@
    	/* Prepare for memory training */
    	prepare_training(ctrl);

-		err = read_training(ctrl);
+		err = receive_enable_calibration(ctrl);
    	if (err)
    		return err;