[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61500 )

Change subject: mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards
......................................................................

mb/google/brya: Lock TPM IRQ pin in brask and brya baseboards

This applies a configuration lock to the TPM IRQ pins for all brya
and brask variants.

BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055:00/pins suggests
GSC_PCH_INT_ODL is locked.

Signed-off-by: Subrata Banik 
Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61500
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: EricR Lai 
---
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
2 files changed, 2 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
index 40d73eb..22b2c70 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -29,7 +29,7 @@
    /* A12 : SATAXPCIE1 ==> CLKREQ_9B */
    PAD_NC(GPP_A12, NONE),
    /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
    /* A14 : USB_OC1# ==> USB_C1_OC_ODL */
    PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
    /* A15 : USB_OC2# ==> USB_C2_OC_ODL */
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index ffc549e..fffbbc8 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -29,7 +29,7 @@
    /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
    PAD_CFG_GPO(GPP_A12, 1, DEEP),
    /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
    /* A14 : USB_OC1# ==> USB_C1_OC_ODL */
    PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
    /* A15 : USB_OC2# ==> USB_C2_OC_ODL */
@@ -458,7 +458,6 @@
 }

static struct gpio_lock_config lockable_brya_gpios[] = {
-	{ GPP_A13, GPIO_LOCK_CONFIG },	/* GSC_PCH_INT_ODL */
    { GPP_E15, GPIO_LOCK_CONFIG },	/* PCH_WP_OD */
    { GPP_F11, GPIO_LOCK_CONFIG },	/* GSPI_PCH_CLK_FPMCU_R */
    { GPP_F13, GPIO_LOCK_CONFIG },	/* GSPI_PCH_D1_FPMCU_D0 */

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.