[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Modify CSE's PCI BAR address

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44211 )

Change subject: soc/intel/cannonlake: Modify CSE's PCI BAR address
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Patch Set 2:
> Patch Set 2:
>
> What about setting the Heci1BarAddress UPD?

Configuring the Heci1BarAddress UPD will close the gap between coreboot & FSP-M. 
I will push the change. Thanks