[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Use common cpu/intel romstage entry

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46658 )

Change subject: soc/intel/xeon_sp: Use common cpu/intel romstage entry
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46658/6/src/soc/intel/xeon_sp/memma... 
File src/soc/intel/xeon_sp/memmap.c:

https://review.coreboot.org/c/coreboot/+/46658/6/src/soc/intel/xeon_sp/memma... 
PS6, Line 37: cbmem_top
I guess FSP provides this pointer? On SKL and CFL, the value for this pointer is MTRR poison (trying to cache it will exhaust all MTRRs and more). I made CB:45930 to fix this on client platforms.