Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14542
-gerrit
commit 216f57632172246188e34a0eea04c5d1556e4989 Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Fri Apr 29 01:34:08 2016 -0500
nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709 Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index f0ee6af..77ae483 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1439,6 +1439,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Back up the Nibble 0 delays for later use */ memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); } + + /* Exit nibble training if current DIMM is not x4 */ + if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0) + break; }
if (_2Ranks) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index c6ec905..ffc6fb2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -184,6 +184,10 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT }
pDCTData->WLCriticalGrossDelayPrevPass = 0x0; + + /* Exit nibble training if current DIMM is not x4 */ + if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0) + break; }
return 0;