6 Dec
2021
6 Dec
'21
8:30 a.m.
Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59918 )
Change subject: Cezanne FSP wrapper: Add UPD entry for eDP tunning ......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/59918/comment/a80d1a42_de2b36ce PS1, Line 111: /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ Does this mean you will apply the same tuning parameters to multiple DPs?
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Gerrit-Project: coreboot
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