[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Change in SaGv options

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30917 )

Change subject: soc/intel/cannonlake: Change in SaGv options
......................................................................

Patch Set 5:

(4 comments)

https://review.coreboot.org/#/c/30917/5/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/30917/5/src/soc/intel/cannonlake/chip.h@103 
PS5, Line 103: 	 * When enabled memory will be training at two or three different frequencies.
line over 80 characters

https://review.coreboot.org/#/c/30917/5/src/soc/intel/cannonlake/chip.h@104 
PS5, Line 104: 	 * for CNL options are as following 
trailing whitespace

https://review.coreboot.org/#/c/30917/5/src/soc/intel/cannonlake/chip.h@105 
PS5, Line 105: 	 * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled 
trailing whitespace

https://review.coreboot.org/#/c/30917/5/src/soc/intel/cannonlake/chip.h@106 
PS5, Line 106: 	 * for others options are as following 
trailing whitespace