Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46373 )
Change subject: haswell/broadwell: Fix typos of `BCLK` ......................................................................
haswell/broadwell: Fix typos of `BCLK`
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Felix Singer felixsinger@posteo.net --- M src/cpu/intel/haswell/haswell_init.c M src/soc/intel/broadwell/cpu.c 2 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index ac5dec6..e03d30f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -207,8 +207,8 @@ return ult; }
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -247,7 +247,7 @@
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
/* Read the calibrated value. */ @@ -259,7 +259,7 @@ return; }
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); }
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index c64af02..179cd43 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -25,8 +25,8 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h>
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -65,7 +65,7 @@
err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code);
/* Read the calibrated value. */ @@ -77,7 +77,7 @@ return; }
- printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); }