Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81851?usp=email )
Change subject: soc/intel/lnl: Do initial Lunar Lake SoC commit till bootblock ......................................................................
soc/intel/lnl: Do initial Lunar Lake SoC commit till bootblock
List of changes:
1. Add required Lunar Lake SoC programming till bootblock 2. Include only required headers into include/soc 3. Include LNL-M related DID, BDF 4. Ref: Processor EDS documents vol1 #734362, vol2 #749160
Change-Id: I90d00628b5342efd9e1d325c12bd6e28f1f47952 Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- A src/soc/intel/lnl_dev/Kconfig A src/soc/intel/lnl_dev/Makefile.mk A src/soc/intel/lnl_dev/bootblock/bootblock.c A src/soc/intel/lnl_dev/bootblock/pch.c A src/soc/intel/lnl_dev/bootblock/report_platform.c A src/soc/intel/lnl_dev/include/soc/bootblock.h A src/soc/intel/lnl_dev/include/soc/espi.h A src/soc/intel/lnl_dev/include/soc/iomap.h A src/soc/intel/lnl_dev/include/soc/p2sb.h A src/soc/intel/lnl_dev/include/soc/pci_devs.h A src/soc/intel/lnl_dev/include/soc/pcr_ids.h A src/soc/intel/lnl_dev/include/soc/pm.h A src/soc/intel/lnl_dev/include/soc/report_platform.h A src/soc/intel/lnl_dev/include/soc/smbus.h A src/soc/intel/lnl_dev/lunarlake/Makefile.mk A src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c A src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h 17 files changed, 1,542 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/81851/1
diff --git a/src/soc/intel/lnl_dev/Kconfig b/src/soc/intel/lnl_dev/Kconfig new file mode 100644 index 0000000..00cedc2 --- /dev/null +++ b/src/soc/intel/lnl_dev/Kconfig @@ -0,0 +1,372 @@ +config SOC_INTEL_LNL_BASE + bool + +config SOC_INTEL_LUNARLAKE + bool + select SOC_INTEL_LNL_BASE + help + Intel Lunarlake support + +if SOC_INTEL_LNL_BASE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_X86 + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_VOLTAGE + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_SUPPORTS_PM_TIMER_EMULATION + select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS + select DEFAULT_X2APIC_LATE_WORKAROUND + select DISPLAY_FSP_VERSION_INFO_2 + select DRIVERS_USB_ACPI + select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 + select FSP_COMPRESS_FSP_S_LZ4 + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW + select FSP_M_XIP + select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + select FSP_USES_CB_DEBUG_EVENT_HANDLER + select GENERIC_GPIO_LIB + select HAVE_DEBUG_RAM_SETUP + select HAVE_FSP_GOP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select LNL_CAR_ENHANCED_NEM + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MP_SERVICES_PPI_V2 + select MRC_SETTINGS_PROTECT + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_4 + select REG_SCRIPT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_EPOC + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CNVI + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR + select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC + select SOC_INTEL_COMMON_BLOCK_IAA + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IRQ + select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 + select SOC_INTEL_COMMON_BLOCK_MEMINIT + select SOC_INTEL_COMMON_BLOCK_OSSE + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI + select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC + select SOC_INTEL_COMMON_BLOCK_USB4 + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_FSP_RESET + select SOC_INTEL_COMMON_PCH_CLIENT + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_IOC + select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_202404_BINDING + select HAVE_X86_64_SUPPORT + select SOC_INTEL_COMMON_BLOCK_PMC_EPOC + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select LUNARLAKE_ENABLE_IBECC + +config LNL_CAR_ENHANCED_NEM + bool + default y if !INTEL_CAR_NEM + select INTEL_CAR_NEM_ENHANCED + select CAR_HAS_SF_MASKS + select COS_MAPPED_TO_MSB + select CAR_HAS_L3_PROTECTED_WAYS + +config MAX_CPUS + int + default 22 + +config DCACHE_RAM_BASE + default 0xfa000000 + +config DCACHE_RAM_SIZE + default 0x200000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x80400 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement + (~1KiB). + +config FSP_TEMP_RAM_SIZE + hex + default 0x80100 + help + The amount of anticipated heap usage in CAR by FSP. + Refer to Platform FSP integration guide document to know + the exact FSP requirement for Heap setup. + +config CHIPSET_DEVICETREE + string + default "soc/intel/lnl_dev/lunarlake/chipset.cb" + +config EXT_BIOS_WIN_BASE + default 0xf8000000 + +config EXT_BIOS_WIN_SIZE + default 0x2000000 + +config IFD_CHIPSET + string + default "ifd2" + +config IED_REGION_SIZE + hex + default 0x400000 + +config HEAP_SIZE + hex + default 0x10000 + +# Intel recommends reserving the PCIe TBT root port resources as below: +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0x6000000 + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x800000000 + +endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config MAX_TBT_ROOT_PORTS + int + default 3 + +config MAX_ROOT_PORTS + int + default 12 + +config MAX_PCIE_CLOCK_SRC + int + default 9 + +config SMM_TSEG_SIZE + hex + default 0x2000000 + +config SMM_RESERVED_SIZE + hex + default 0x200000 + +config PCR_BASE_ADDRESS + hex + default 0xe0000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config ECAM_MMCONF_BASE_ADDRESS + default 0xc0000000 + +config CPU_BCLK_MHZ + int + default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + default 120 + +config CPU_XTAL_HZ + default 38400000 + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 2 + +config SOC_INTEL_I2C_DEV_MAX + int + default 6 + +config SOC_INTEL_I3C_DEV_MAX + int + default 2 + +config SOC_INTEL_UART_DEV_MAX + int + default 3 + +config SOC_INTEL_USB2_DEV_MAX + int + default 10 + +config SOC_INTEL_USB3_DEV_MAX + int + default 2 + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe03e000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +config VBT_DATA_SIZE_KB + int + default 9 + +# Clock divider parameters for 115200 baud rate +# Baudrate = (UART source clcok * M) /(N *16) +# LNL UART source clock: 120MHz +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x25a + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0x7fff + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VBOOT_X86_SHA256_ACCELERATION + +# Default hash block size is 1KiB. Increasing it to 4KiB to improve +# hashing time as well as read time. +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x1000 + +config CBFS_SIZE + hex + default 0x200000 + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x2000 + +config CONSOLE_CBMEM_BUFFER_SIZE + hex + default 0x40000 + +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_4/lunarlake/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/LunarLakeFspBinPkg/Fsp.fd" + +config SOC_INTEL_DEBUG_CONSENT_2 + int "Debug Consent" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 3 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual + +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config MRC_CHANNEL_WIDTH + int + default 16 + +config SOC_INTEL_CRASHLOG + def_bool n + select SOC_INTEL_COMMON_BLOCK_CRASHLOG + select ACPI_BERT + help + Enables CrashLog. + +config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET + hex + default 0x800000 + +config FSP_PUBLISH_MBP_HOB + bool + default n if CHROMEOS + default y + help + This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. + Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. + +config SOC_INTEL_UFS_CLK_FREQ_HZ + int + default 38400000 + +config LUNARLAKE_ENABLE_IBECC + bool "Enable IBECC" + help + Enables In Band Error Correction Code. It's only needed for endurance testing + and therefore not always required. + default n + +endif diff --git a/src/soc/intel/lnl_dev/Makefile.mk b/src/soc/intel/lnl_dev/Makefile.mk new file mode 100644 index 0000000..e080444 --- /dev/null +++ b/src/soc/intel/lnl_dev/Makefile.mk @@ -0,0 +1,62 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_INTEL_LNL_BASE),y) + +subdirs-$(CONFIG_SOC_INTEL_LUNARLAKE) += lunarlake +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c +bootblock-y += p2sb.c +bootblock-y += soc_info.c +bootblock-y += systemagent.c + +romstage-y += espi.c +romstage-y += reset.c +romstage-y += soc_info.c +romstage-y += ../../../cpu/intel/car/romstage.c +romstage-y += romstage.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-y += lockdown.c +ramstage-y += me.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += retimer.c +ramstage-y += soundwire.c +ramstage-y += systemagent.c +ramstage-y += tcss.c +ramstage-y += xhci.c +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c +ramstage-y += soc_info.c + +smm-y += elog.c +smm-y += p2sb.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += uart.c +smm-y += xhci.c +smm-y += soc_info.c + +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev/include + +CFLAGS_common += -Wno-error=int-conversion +endif diff --git a/src/soc/intel/lnl_dev/bootblock/bootblock.c b/src/soc/intel/lnl_dev/bootblock/bootblock.c new file mode 100644 index 0000000..9f113ef --- /dev/null +++ b/src/soc/intel/lnl_dev/bootblock/bootblock.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/bootblock.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_soc_die_early_init(); +} + +void bootblock_soc_init(void) +{ + report_platform_info(); + bootblock_pch_init(); +} diff --git a/src/soc/intel/lnl_dev/bootblock/pch.c b/src/soc/intel/lnl_dev/bootblock/pch.c new file mode 100644 index 0000000..9d7c359 --- /dev/null +++ b/src/soc/intel/lnl_dev/bootblock/pch.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <intelblocks/systemagent.h> +#include <intelblocks/tco.h> +#include <intelblocks/uart.h> +#include <soc/bootblock.h> +#include <soc/espi.h> +#include <soc/iomap.h> +#include <soc/p2sb.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/pch.h> + +static void soc_config_pwrmbase(void) +{ + /* + * Assign Resources to PWRMBASE + * Clear BIT 1-2 Command Register + */ + pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Program PWRM Base */ + pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* Enable PWRM in PMC */ + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); +} + +void pch_early_iorange_init(void) +{ + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + + /* IO Decode Range */ + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); + + /* IO Decode Enable */ + lpc_enable_fixed_io_ranges(io_enables); + + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} + +void bootblock_pch_early_init(void) +{ + soc_die_early_sa_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ + p2sb_enable_bar(); + p2sb2_enable_bar(); + p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + + /* + * Enabling SoC PMC PWRM Base for accessing + * Global Reset Cause Register. + */ + soc_config_pwrmbase(); +} + +void soc_die_early_sa_init(void) +{ + const struct sa_mmio_descriptor soc_fixed_pci_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + }; + + bootblock_systemagent_early_init(); + + /* Enable MCHBAR early, needed by IOC driver */ + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); +} + +void bootblock_soc_die_early_init(void) +{ + /* + * Ensure performing SA related programming including MCHBAR prior to accessing + * IOC driver. + */ + soc_die_early_sa_init(); + + bootblock_pch_early_init(); + + fast_spi_cache_bios_region(); + pch_early_iorange_init(); + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + uart_bootblock_init(); +} + +static void soc_config_acpibase(void) +{ + uint32_t pmc_reg_value; + uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE; + + pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); + + if (pmc_reg_value != 0xffffffff) { + /* Disable Io Space before changing the address */ + pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); + /* Program ABASE in PSF8 PMC space BAR4*/ + pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, + ACPI_BASE_ADDRESS); + /* Enable IO Space */ + pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); + } +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, + * GPE0_STS, GPE0_EN registers. + */ + soc_config_acpibase(); + + /* Set up GPE configuration */ + pmc_gpe_init(); + + enable_rtc_upper_bank(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); +} diff --git a/src/soc/intel/lnl_dev/bootblock/report_platform.c b/src/soc/intel/lnl_dev/bootblock/report_platform.c new file mode 100644 index 0000000..0082c28 --- /dev/null +++ b/src/soc/intel/lnl_dev/bootblock/report_platform.c @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/name.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <intelblocks/cpulib.h> +#include <soc/bootblock.h> +#include <soc/pci_devs.h> +#include <soc/report_platform.h> + +static inline uint8_t get_dev_revision(pci_devfn_t dev) +{ + return pci_read_config8(dev, PCI_REVISION_ID); +} + +static inline uint16_t get_dev_id(pci_devfn_t dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static void report_cache_info(void) +{ + int cache_level = CACHE_L3; + struct cpu_cache_info info; + + if (!fill_cpu_cache_info(cache_level, &info)) + return; + + printk(BIOS_INFO, "Cache: Level %d: ", cache_level); + printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n", + info.num_ways, info.physical_partitions, info.line_size, info.num_sets); + + printk(BIOS_INFO, "Cache size = %zu MiB\n", get_cache_size(&info)/MiB); +} + +static enum core_type get_soc_cpu_type(void) +{ + if (cpu_is_hybrid_supported()) + return cpu_get_cpu_type(); + else + return CPUID_CORE_TYPE_INTEL_CORE; +} + +static void report_cpu_info(void) +{ + u32 i, cpu_id, cpu_feature_flag; + char cpu_name[49]; + int vt, txt, aes; + static const char *const mode[] = {"NOT ", ""}; + const char *cpu_type = "Unknown"; + + fill_processor_name(cpu_name); + cpu_id = cpu_get_cpuid(); + + /* Look for string to match the name */ + for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { + if (cpu_table[i].cpuid == cpu_id) { + cpu_type = cpu_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); + printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", + cpu_id, cpu_type, get_current_microcode_rev()); + + printk(BIOS_DEBUG, "CPU Type: %s\n", get_soc_cpu_type() == CPUID_CORE_TYPE_INTEL_CORE ? "core" : "atom"); + + cpu_feature_flag = cpu_get_feature_flags_ecx(); + aes = !!(cpu_feature_flag & CPUID_AES); + txt = !!(cpu_feature_flag & CPUID_SMX); + vt = !!(cpu_feature_flag & CPUID_VMX); + printk(BIOS_DEBUG, + "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); + + report_cache_info(); +} + +static void report_mch_info(void) +{ + int i; + pci_devfn_t dev = PCI_DEV_ROOT; + uint16_t mchid = get_dev_id(dev); + const char *mch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(mch_table); i++) { + if (mch_table[i].mchid == mchid) { + mch_type = mch_table[i].name; + break; + } + } + + printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", + mchid, get_dev_revision(dev), mch_type); +} + +static void report_pch_info(void) +{ + int i; + pci_devfn_t dev = PCI_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); + const char *pch_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].espiid == espiid) { + pch_type = pch_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", + espiid, get_dev_revision(dev), pch_type); +} + +static void report_igd_info(void) +{ + int i; + pci_devfn_t dev = PCI_DEV_IGD; + uint16_t igdid = get_dev_id(dev); + const char *igd_type = "Unknown"; + + for (i = 0; i < ARRAY_SIZE(igd_table); i++) { + if (igd_table[i].igdid == igdid) { + igd_type = igd_table[i].name; + break; + } + } + printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", + igdid, get_dev_revision(dev), igd_type); +} + +void report_platform_info(void) +{ + report_cpu_info(); + report_mch_info(); + report_pch_info(); + report_igd_info(); +} diff --git a/src/soc/intel/lnl_dev/include/soc/bootblock.h b/src/soc/intel/lnl_dev/include/soc/bootblock.h new file mode 100644 index 0000000..89e3e8f --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/bootblock.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_BOOTBLOCK_H_ +#define _SOC_INTEL_LNL_BOOTBLOCK_H_ + +/* Bootblock pre console init programming */ +void bootblock_soc_die_early_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); + +#endif //_SOC_INTEL_LNL_BOOTBLOCK_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/espi.h b/src/soc/intel/lnl_dev/include/soc/espi.h new file mode 100644 index 0000000..ea2f822 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/espi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_ESPI_H_ +#define _SOC_INTEL_LNL_ESPI_H_ + +/* PCI Configuration Space (D31:F0): ESPI */ +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define SERIRQ_CNTL 0x64 +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ +#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ +#define PCCTL 0xE0 /* PCI Clock Control */ +#define CLKRUN_EN (1 << 0) + +#endif //_SOC_LUNARLAKE_SOC_INTEL_LNL diff --git a/src/soc/intel/lnl_dev/include/soc/iomap.h b/src/soc/intel/lnl_dev/include/soc/iomap.h new file mode 100644 index 0000000..bd72e2e --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/iomap.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_IOMAP_H_ +#define _SOC_INTEL_LNL_IOMAP_H_ + +#include <soc/pcr_ids.h> +#include <platform_soc_defs.h> + +/* + * Memory-mapped I/O registers. + */ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD800000 +#define PCH_PRESERVED_BASE_SIZE 0x01000000 + +#define MCH_BASE_ADDRESS 0xFEDC0000 +#define MCH_BASE_SIZE 0x20000 + +#define EP_BASE_ADDRESS 0xFEDA1000 +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_ADDRESS 0xFED80000 +#define EDRAM_BASE_SIZE 0x4000 + +#define HPET_BASE_ADDRESS 0xFED00000 + +//PMC MBAR 64KB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 +#define PCH_PWRM_BASE_SIZE 0x10000 + +#define GPIO_BASE_SIZE 0x10000 + +#define HECI1_BASE_ADDRESS 0xFEDA2000 + + +#define UART_BASE_SIZE 0x1000 +#define UART_BASE_0_ADDRESS 0xFE03E000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define EARLY_GSPI_BASE_ADDRESS 0xFE030000 + +#define EARLY_I2C_BASE_ADDRESS 0xFE020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define SPI_BASE_ADDRESS 0xFE010000 + +#define PCH_SECOND_PCR_ABOVE_4G_BASE_ADDR 0x3FFF0000000 + +/* + * I/O port address space + */ +#define ACPI_BASE_ADDRESS 0x1800 +#define ACPI_BASE_SIZE 0x100 + +#define TCO_BASE_ADDRESS 0x400 +#define TCO_BASE_SIZE 0x20 +#endif //_SOC_INTEL_LNL_IOMAP_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/p2sb.h b/src/soc/intel/lnl_dev/include/soc/p2sb.h new file mode 100644 index 0000000..6a8610f --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/p2sb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_P2SB_H_ +#define _SOC_INTEL_LNL_P2SB_H_ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0x220 + +extern struct device_operations soc_p2sb_ops; + +#endif //_SOC_INTEL_LNL_P2SB_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/pci_devs.h b/src/soc/intel/lnl_dev/include/soc/pci_devs.h new file mode 100644 index 0000000..80ee26a --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pci_devs.h @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PCI_DEVS_H_ +#define _SOC_INTEL_LNL_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCI_DEVFN(slot, func) PCI_DEVFN(PCI_DEV_SLOT_ ## slot, func) +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCI_DEV(slot, func) pcidev_path_on_root_debug(_PCI_DEVFN(slot, func), __func__) +#else +#define _PCI_DEV(slot, func) PCI_DEV(0, PCI_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ +#define PCI_DEV_SLOT_ROOT 0x00 +#define PCI_DEVFN_ROOT _PCI_DEVFN(ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define PCI_DEV_ROOT _PCI_DEV(ROOT, 0) +#endif + +#define PCI_DEV_SLOT_IGD 0x02 +#define PCI_DEVFN_IGD _PCI_DEVFN(IGD, 0) +#define PCI_DEV_IGD _PCI_DEV(IGD, 0) + +#define PCI_DEV_SLOT_DPTF 0x04 +#define PCI_DEVFN_DPTF _PCI_DEVFN(DPTF, 0) +#define PCI_DEV_DPTF _PCI_DEV(DPTF, 0) + +#define PCI_DEV_SLOT_IPU 0x05 +#define PCI_DEVFN_IPU _PCI_DEVFN(IPU, 0) +#define PCI_DEV_IPU _PCI_DEV(IPU, 0) + +#define PCI_DEV_SLOT_TBT 0x07 +#define PCI_DEVFN_TBT(x) _PCI_DEVFN(TBT, (x)) +#if CONFIG(SOC_INTEL_LUNARLAKE) +#define NUM_TBT_FUNCTIONS 3 +#endif +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define NUM_TBT_FUNCTIONS 4 +#define PCI_DEVFN_TBT3 _PCI_DEVFN(TBT, 3) +#define PCI_DEV_TBT3 _PCI_DEV(TBT, 3) +#endif +#define PCI_DEVFN_TBT0 _PCI_DEVFN(TBT, 0) +#define PCI_DEVFN_TBT1 _PCI_DEVFN(TBT, 1) +#define PCI_DEVFN_TBT2 _PCI_DEVFN(TBT, 2) +#define PCI_DEV_TBT0 _PCI_DEV(TBT, 0) +#define PCI_DEV_TBT1 _PCI_DEV(TBT, 1) +#define PCI_DEV_TBT2 _PCI_DEV(TBT, 2) + +#define PCI_DEV_SLOT_NPU 0xb +#define PCI_DEVFN_NPU _PCI_DEVFN(NPU, 0) +#define PCI_DEV_NPU _PCI_DEV(NPU, 0) + +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_IAA 0xc +#define PCI_DEVFN_IAA _PCI_DEVFN(IAA, 0) +#define PCI_DEV_IAA _PCI_DEV(IAA, 0) +#endif + +#define PCI_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define PCI_DEVFN_TCSS_DMA(x) _PCI_DEVFN(TCSS, ((x) + 2)) +#define PCI_DEVFN_TCSS_XHCI _PCI_DEVFN(TCSS, 0) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEVFN_TCSS_XDCI _PCI_DEVFN(TCSS, 1) +#define PCI_DEV_TCSS_XDCI _PCI_DEV(TCSS, 1) +#endif +#define PCI_DEVFN_TCSS_DMA0 _PCI_DEVFN(TCSS, 2) +#define PCI_DEVFN_TCSS_DMA1 _PCI_DEVFN(TCSS, 3) +#define PCI_DEV_TCSS_XHCI _PCI_DEV(TCSS, 0) +#define PCI_DEV_TCSS_DMA0 _PCI_DEV(TCSS, 2) +#define PCI_DEV_TCSS_DMA1 _PCI_DEV(TCSS, 3) + +#define PCI_DEV_SLOT_VMD 0x0e +#define PCI_DEVFN_VMD _PCI_DEVFN(VMD, 0) +#define PCI_DEV_VMD _PCI_DEV(VMD, 0) + +#define PCI_DEV_SLOT_THC 0x10 +#define PCI_DEVFN_THC0 _PCI_DEVFN(THC, 0) +#define PCI_DEVFN_THC1 _PCI_DEVFN(THC, 1) +#define PCI_DEV_THC0 _PCI_DEV(THC, 0) +#define PCI_DEV_THC1 _PCI_DEV(THC, 1) + +#define PCI_DEV_SLOT_I3C 0x11 +#define PCI_DEVFN_I3C1 _PCI_DEVFN(I3C, 0) +#define PCI_DEVFN_I3C2 _PCI_DEVFN(I3C, 2) +#define PCI_DEV_I3C1 _PCI_DEV(I3C, 0) +#define PCI_DEV_I3C2 _PCI_DEV(I3C, 2) + +#define PCI_DEV_SLOT_ISH 0x12 +#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) +#define PCI_DEVFN_P2SB2 _PCI_DEVFN(ISH, 1) +#if CONFIG(SOC_INTEL_LUNARLAKE) +#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) +#define PCI_DEVFN_UFS _PCI_DEVFN(ISH, 7) +#define PCI_DEV_GSPI2 _PCI_DEV(ISH, 6) +#define PCI_DEV_UFS _PCI_DEV(ISH, 7) +#endif +#define PCI_DEV_ISH _PCI_DEV(ISH, 0) +#define PCI_DEV_P2SB2 _PCI_DEV(ISH, 1) + +#define PCI_DEV_SLOT_OSSE 0x13 +#define PCI_DEVFN_OSSE1 _PCI_DEVFN(OSSE, 0) +#define PCI_DEVFN_OSSE2 _PCI_DEVFN(OSSE, 1) +#define PCI_DEVFN_OSSE3 _PCI_DEVFN(OSSE, 2) +#define PCI_DEV_OSSE1 _PCI_DEV(OSSE, 0) +#define PCI_DEV_OSSE2 _PCI_DEV(OSSE, 1) +#define PCI_DEV_OSSE3 _PCI_DEV(OSSE, 2) + +#define PCI_DEV_SLOT_XHCI 0x14 +#define PCI_DEVFN_XHCI _PCI_DEVFN(XHCI, 0) +#define PCI_DEVFN_USBOTG _PCI_DEVFN(XHCI, 1) +#define PCI_DEVFN_SRAM _PCI_DEVFN(XHCI, 2) +#define PCI_DEVFN_CNVI_WIFI _PCI_DEVFN(XHCI, 3) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEVFN_IEH _PCI_DEVFN(XHCI, 5) +#define PCI_DEVFN_CNVI_BT _PCI_DEVFN(XHCI, 7) +#define PCI_DEV_IEH _PCI_DEV(XHCI, 5) +#define PCI_DEV_CNVI_BT _PCI_DEV(XHCI, 7) +#endif +#define PCI_DEV_XHCI _PCI_DEV(XHCI, 0) +#define PCI_DEV_USBOTG _PCI_DEV(XHCI, 1) +#define PCI_DEV_SRAM _PCI_DEV(XHCI, 2) +#define PCI_DEV_CNVI_WIFI _PCI_DEV(XHCI, 3) + +#define PCI_DEV_SLOT_SIO0 0x15 +#define PCI_DEVFN_I2C0 _PCI_DEVFN(SIO0, 0) +#define PCI_DEVFN_I2C1 _PCI_DEVFN(SIO0, 1) +#define PCI_DEVFN_I2C2 _PCI_DEVFN(SIO0, 2) +#define PCI_DEVFN_I2C3 _PCI_DEVFN(SIO0, 3) +#define PCI_DEV_I2C0 _PCI_DEV(SIO0, 0) +#define PCI_DEV_I2C1 _PCI_DEV(SIO0, 1) +#define PCI_DEV_I2C2 _PCI_DEV(SIO0, 2) +#define PCI_DEV_I2C3 _PCI_DEV(SIO0, 3) + +#define PCI_DEV_SLOT_CSE 0x16 +#define PCI_DEVFN_CSE _PCI_DEVFN(CSE, 0) +#define PCI_DEVFN_CSE_2 _PCI_DEVFN(CSE, 1) +#define PCI_DEVFN_CSE_IDER _PCI_DEVFN(CSE, 2) +#define PCI_DEVFN_CSE_KT _PCI_DEVFN(CSE, 3) +#define PCI_DEVFN_CSE_3 _PCI_DEVFN(CSE, 4) +#define PCI_DEVFN_CSE_4 _PCI_DEVFN(CSE, 5) +#define PCI_DEV_CSE _PCI_DEV(CSE, 0) +#define PCI_DEV_CSE_2 _PCI_DEV(CSE, 1) +#define PCI_DEV_CSE_IDER _PCI_DEV(CSE, 2) +#define PCI_DEV_CSE_KT _PCI_DEV(CSE, 3) +#define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4) +#define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5) +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_CSE_WLAN _PCI_DEV(CSE, 7) +#endif + +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_UFS 0x17 +#define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0) +#define PCI_DEV_UFS _PCI_DEV(UFS, 0) +#endif +#define PCI_DEV_SLOT_ESE 0x18 +#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) +#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) +#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2) +#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0) +#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1) +#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2) + +#define PCI_DEV_SLOT_SIO1 0x19 +#define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) +#define PCI_DEVFN_I2C5 _PCI_DEVFN(SIO1, 1) +#define PCI_DEVFN_UART2 _PCI_DEVFN(SIO1, 2) +#define PCI_DEV_I2C4 _PCI_DEV(SIO1, 0) +#define PCI_DEV_I2C5 _PCI_DEV(SIO1, 1) +#define PCI_DEV_UART2 _PCI_DEV(SIO1, 2) + +#define PCI_DEV_SLOT_PCIE_1 0x1c +#define PCI_DEVFN_PCIE1 _PCI_DEVFN(PCIE_1, 0) +#define PCI_DEVFN_PCIE2 _PCI_DEVFN(PCIE_1, 1) +#define PCI_DEVFN_PCIE3 _PCI_DEVFN(PCIE_1, 2) +#define PCI_DEVFN_PCIE4 _PCI_DEVFN(PCIE_1, 3) +#define PCI_DEVFN_PCIE5 _PCI_DEVFN(PCIE_1, 4) +#define PCI_DEVFN_PCIE6 _PCI_DEVFN(PCIE_1, 5) +#define PCI_DEV_PCIE1 _PCI_DEV(PCIE_1, 0) +#define PCI_DEV_PCIE2 _PCI_DEV(PCIE_1, 1) +#define PCI_DEV_PCIE3 _PCI_DEV(PCIE_1, 2) +#define PCI_DEV_PCIE4 _PCI_DEV(PCIE_1, 3) +#define PCI_DEV_PCIE5 _PCI_DEV(PCIE_1, 4) +#define PCI_DEV_PCIE6 _PCI_DEV(PCIE_1, 5) + +#if CONFIG(SOC_INTEL_PANTHERLAKE) +#define PCI_DEV_SLOT_PCIE_2 0x6 +#define PCI_DEVFN_PCIE9 _PCI_DEVFN(PCIE_2, 0) +#define PCI_DEVFN_PCIE10 _PCI_DEVFN(PCIE_2, 1) +#define PCI_DEVFN_PCIE11 _PCI_DEVFN(PCIE_2, 2) +#define PCI_DEV_PCIE9 _PCI_DEV(PCIE_2, 0) +#define PCI_DEV_PCIE10 _PCI_DEV(PCIE_2, 1) +#define PCI_DEV_PCIE11 _PCI_DEV(PCIE_2, 2) + +#define PCI_DEV_SLOT_PCIE_3 0x1 +#define PCI_DEVFN_PCIE12 _PCI_DEVFN(PCIE_3, 0) +#define PCI_DEV_PCIE12 _PCI_DEV(PCIE_3, 0) +#endif + +#define PCI_DEV_SLOT_SIO2 0x1e +#define PCI_DEVFN_UART0 _PCI_DEVFN(SIO2, 0) +#define PCI_DEVFN_UART1 _PCI_DEVFN(SIO2, 1) +#define PCI_DEVFN_GSPI0 _PCI_DEVFN(SIO2, 2) +#define PCI_DEVFN_GSPI1 _PCI_DEVFN(SIO2, 3) +#define PCI_DEVFN_TSN1 _PCI_DEVFN(SIO2, 4) +#define PCI_DEVFN_TSN2 _PCI_DEVFN(SIO2, 5) +#define PCI_DEV_UART0 _PCI_DEV(SIO2, 0) +#define PCI_DEV_UART1 _PCI_DEV(SIO2, 1) +#define PCI_DEV_GSPI0 _PCI_DEV(SIO2, 2) +#define PCI_DEV_GSPI1 _PCI_DEV(SIO2, 3) +#define PCI_DEV_TSN1 _PCI_DEV(SIO2, 4) +#define PCI_DEV_TSN2 _PCI_DEV(SIO2, 5) + +#define PCI_DEV_SLOT_ESPI 0x1f +#define PCI_DEVFN_ESPI _PCI_DEVFN(ESPI, 0) +#define PCI_DEVFN_P2SB _PCI_DEVFN(ESPI, 1) +#define PCI_DEVFN_PMC _PCI_DEVFN(ESPI, 2) +#define PCI_DEVFN_HDA _PCI_DEVFN(ESPI, 3) +#define PCI_DEVFN_SMBUS _PCI_DEVFN(ESPI, 4) +#define PCI_DEVFN_SPI _PCI_DEVFN(ESPI, 5) +#define PCI_DEVFN_GBE _PCI_DEVFN(ESPI, 6) +#define PCI_DEVFN_NPK _PCI_DEVFN(ESPI, 7) +#define PCI_DEV_ESPI _PCI_DEV(ESPI, 0) +#define PCI_DEV_P2SB _PCI_DEV(ESPI, 1) + +#if !ENV_RAMSTAGE +/* + * PCI_DEV_PMC is intentionally not defined in RAMSTAGE since PMC device gets + * hidden from PCI bus after call to FSP-S. This leads to resource allocator + * dropping it from the root bus as unused device. All references to PCI_DEV_PMC + * would then return NULL and can go unnoticed if not handled properly. Since, + * this device does not have any special chip config associated with it, it is + * okay to not provide the definition for it in ramstage. + */ +#define PCI_DEV_PMC _PCI_DEV(ESPI, 2) +#endif + +#define PCI_DEV_HDA _PCI_DEV(ESPI, 3) +#define PCI_DEV_SMBUS _PCI_DEV(ESPI, 4) +#define PCI_DEV_SPI _PCI_DEV(ESPI, 5) +#define PCI_DEV_GBE _PCI_DEV(ESPI, 6) +#define PCI_DEV_NPK _PCI_DEV(ESPI, 7) + +#endif + +/* for common code */ +#define MIN_PCH_SLOT PCI_DEV_SLOT_THC +#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE +#define PCH_DEVFN_CSE PCI_DEVFN_CSE +#define PCH_DEV_CSE PCI_DEV_CSE +#define PCH_DEV_SPI PCI_DEV_SPI +#define PCH_DEV_LPC PCI_DEV_ESPI +#define PCH_DEV_P2SB PCI_DEV_P2SB +#define PCH_DEV_P2SB2 PCI_DEV_P2SB2 +#define PCH_DEV_SMBUS PCI_DEV_SMBUS +#define PCH_DEV_XHCI PCI_DEV_XHCI +#define PCH_DEVFN_XHCI PCI_DEVFN_XHCI +#define PCH_DEVFN_PMC PCI_DEVFN_PMC +#define PCH_DEV_SLOT_ISH PCI_DEV_SLOT_ISH +#define SA_DEV_ROOT PCI_DEV_ROOT +#define SA_DEVFN_ROOT PCI_DEVFN_ROOT +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0 +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 +#define SA_DEV_IGD PCI_DEV_IGD +#define SA_DEVFN_IGD PCI_DEVFN_IGD diff --git a/src/soc/intel/lnl_dev/include/soc/pcr_ids.h b/src/soc/intel/lnl_dev/include/soc/pcr_ids.h new file mode 100644 index 0000000..7c87877 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pcr_ids.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PCR_H +#define _SOC_INTEL_LNL_PCR_H +/* + * Port ids + */ +#include <platform_soc_defs.h> + +#endif //_SOC_INTEL_LNL_PCR_H diff --git a/src/soc/intel/lnl_dev/include/soc/pm.h b/src/soc/intel/lnl_dev/include/soc/pm.h new file mode 100644 index 0000000..baf4956 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/pm.h @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PM_H_ +#define _SOC_INTEL_LNL_PM_H_ + +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) +#define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) +#define APMC_EN (1 << 5) +#define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN_BIT 13 +#define PME_B0_EN (1 << PME_B0_EN_BIT) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) + +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on TCO events, unless enabled in common code + * - on microcontroller writes (io 0x62/0x66) + */ +#define ENABLE_SMI_PARAMS \ + (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) + +#define PSS_RATIO_STEP 2 +#define PSS_MAX_ENTRIES 8 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#if !defined(__ACPI__) + +#include <acpi/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); + +/* STM Support */ +uint16_t get_pmbase(void); +#endif /* !defined(__ACPI__) */ +#endif //_SOC_INTEL_LNL_PM_H_ diff --git a/src/soc/intel/lnl_dev/include/soc/report_platform.h b/src/soc/intel/lnl_dev/include/soc/report_platform.h new file mode 100644 index 0000000..6038355 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/report_platform.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_PLATFORM_H_ +#define _SOC_INTEL_LNL_PLATFORM_H_ + +#include <console/console.h> +#include <platform_soc_defs.h> + +enum core_type { + CPUID_RESERVED_1 = 0x10, + CPUID_CORE_TYPE_INTEL_ATOM = 0x20, + CPUID_RESERVED_2 = 0x30, + CPUID_CORE_TYPE_INTEL_CORE = 0x40, + CPUID_UNKNOWN = 0xff, +}; + +__attribute__((weak)) struct { + u32 cpuid; + const char *name; +} cpu_table[SOC_PLATFORM_CPUID_MAX] = { +}; + +__attribute__((weak)) struct { + u16 mchid; + const char *name; +} mch_table[SOC_PLATFORM_MCH_MAX] = { +}; + +__attribute__((weak)) struct { + u16 espiid; + const char *name; +} pch_table[SOC_PLATFORM_PCH_MAX] = { +}; + +__attribute__((weak)) struct { + u16 igdid; + const char *name; +} igd_table[SOC_PLATFORM_IGD_MAX] = { +}; + +#endif /* _SOC_INTEL_LNL_PLATFROM_H_ */ diff --git a/src/soc/intel/lnl_dev/include/soc/smbus.h b/src/soc/intel/lnl_dev/include/soc/smbus.h new file mode 100644 index 0000000..195e7c9 --- /dev/null +++ b/src/soc/intel/lnl_dev/include/soc/smbus.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_LNL_SMBUS_H_ +#define _SOC_INTEL_LNL_SMBUS_H_ + +#include <intelpch/smbus.h> + +#endif //_SOC_SMBUS_H_ diff --git a/src/soc/intel/lnl_dev/lunarlake/Makefile.mk b/src/soc/intel/lnl_dev/lunarlake/Makefile.mk new file mode 100644 index 0000000..000c566 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/Makefile.mk @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_INTEL_LUNARLAKE),y) + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gpio.c + +bootblock-y += bootstage/report_platform.c +bootblock-y += elog.c +bootblock-y += gpio.c +bootblock-y += systemagent.c + +romstage-y += elog.c +romstage-y += gpio.c +romstage-y += meminit.c +romstage-y += pcie_rp.c + +romstage-y += romstage/fsp_params.c +romstage-y += romstage/systemagent.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-y += elog.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += pcie_rp.c +ramstage-y += systemagent.c + +smm-y += elog.c +smm-y += gpio.c + +CPPFLAGS_common += -I$(src)/soc/intel/lnl_dev/lunarlake/include +endif diff --git a/src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c b/src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c new file mode 100644 index 0000000..4f5554b --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/bootstage/report_platform.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/intel/cpu_ids.h> +#include <device/pci_ids.h> + +struct { + u32 cpuid; + const char *name; +} cpu_table[] = { + { CPUID_LUNARLAKE_A0_1, "Lunarlake A0" }, + { CPUID_LUNARLAKE_A0_2, "Lunarlake A0" }, +}; + +struct { + u16 mchid; + const char *name; +} mch_table[] = { + { PCI_DID_INTEL_LNL_M_ID, "LunarLake M" }, +}; + +struct { + u16 espiid; + const char *name; +} pch_table[] = { + { PCI_DID_INTEL_LNL_ESPI_0, "Lunarlake SOC" }, + { PCI_DID_INTEL_LNL_ESPI_1, "Lunarlake SOC-P SuperSKU" }, + { PCI_DID_INTEL_LNL_ESPI_2, "Lunarlake SOC-P Premium" }, + { PCI_DID_INTEL_LNL_ESPI_3, "Lunarlake SOC-P Base" }, + { PCI_DID_INTEL_LNL_ESPI_4, "Lunarlake SOC" }, + { PCI_DID_INTEL_LNL_ESPI_5, "Lunarlake SOC" }, + { PCI_DID_INTEL_LNL_ESPI_6, "Lunarlake SOC-M SuperSKU" }, + { PCI_DID_INTEL_LNL_ESPI_7, "Lunarlake SOC-M Premium" }, +}; + +struct { + u16 igdid; + const char *name; +} igd_table[] = { + { PCI_DID_INTEL_LNL_M_GT2, "Lunarlake-M GT2" }, +}; diff --git a/src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h b/src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h new file mode 100644 index 0000000..fcbc5a3 --- /dev/null +++ b/src/soc/intel/lnl_dev/lunarlake/include/platform_soc_defs.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_LUNARLAKE_PLATFORM_SOC_DEFS_H_ +#define _SOC_LUNARLAKE_PLATFORM_SOC_DEFS_H_ + +/* + * SoC SSDT Info. + */ +#define PMC_FILL_SSDT "Intel(R) Lunar Lake IPC Controller" + +/* + * PCH INFO. + */ +#define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xB00 + +/* + * SoC Report Info. + */ +#define MAX_USB2_PORT 6 +#define MAX_TCSS_PORT 3 +#define MAX_TBT_PCIE_PORT 3 +#define MAX_PCIE_PORT 6 +#define MAX_PCIE_CLOCK 6 + +/* + * Platform Report Info. + */ +#define SOC_PLATFORM_CPUID_MAX 2 +#define SOC_PLATFORM_MCH_MAX 1 +#define SOC_PLATFORM_PCH_MAX 8 +#define SOC_PLATFORM_IGD_MAX 1 + +/* + * GPIO INFO. + */ +#define CROS_GPIO_NAME "INTC105D" +#define CROS_GPIO_DEVICE_NAME "INTC105D:00" + +/* + * Memory-mapped I/O registers. + */ +//SAF BAR 32MB + Unsused 96MB +#define SAF_BASE_ADDRESS 0xD8000000 +#define SAF_BASE_SIZE 0x8000000 + +//DMI3Bar 8KB +#define DMI_BASE_ADDRESS 0xFED90000 +#define DMI_BASE_SIZE 0x2000 + +//OneSiliconPkg/Fru/LnlCDie/Vtd/Library/PeiDxeSmmVtdInfoFruLib/VtdInfoFruLib.c +//VTD BAR 512KB +#define VTD_BASE_ADDRESS 0xFC800000 +#define VTD_BASE_SIZE 0x00080000 + +// GFX VT-d 64KB +#define GFXVT_BASE_ADDRESS VTD_BASE_ADDRESS +#define GFXVT_BASE_SIZE 0x00010000 + +// Non-GFX VT-d 64KB +#define NONGFXVT_BASE_ADDRESS 0xFC810000 +#define NONGFXVT_BASE_SIZE 0x00010000 + +//IOC VT-d 64KB +#define IOCVTD_BASE_ADDRESS 0xFC820000 +#define IOCVTD_BASE_SIZE 0x00010000 + +#define REGBAR 0x5400 + +//REGBAR 128MB +#define REG_BASE_ADDRESS 0xD0000000 +#define REG_BASE_SIZE (128 * MiB) //REGBAR 128MB + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (256 * MiB) ///< 256MB + +//PCH P2SB2 256MB +#define P2SB2_BAR 0xDF000000 +#define P2SB2_SIZE (256 * MiB) ///< 256MB, used by SBREG_BAR 20-bit address platforms + +#define PID_IOM 0x80 +#define IOM_BASE_ADDR 0xE0000000 + (PID_IOM << 16) +#define IOM_BASE_SIZE 0x1600 +#define IOM_BASE_ADDR_MAX 0xE08015FF + +/* + * Port ids + */ +#define PID_GPIOCOM0 0x70 +#define PID_GPIOCOM1 0x71 +#define PID_GPIOCOM2 0x72 +#define PID_GPIOCOM3 0x73 +#define PID_GPIOCOM4 0x74 +#define PID_GPIOCOM5 0x75 + +#define PID_PSF8 0xB8 +#define PID_PSF7 0xB7 +#define PID_PSF6 0xB6 +#define PID_PSF5 0xB5 +#define PID_PSF4 0xB4 +#define PID_PSF3 0xB3 +#define PID_PSF2 0xB2 +#define PID_PSF1 0xB1 +#define PID_PSF0 0xB0 + +#define PID_CSME0 0x40 +#define PID_PSTH 0x6A +#define PID_ITSS 0x69 +#define PID_RTC 0x6C +#define PID_ISCLK 0x64 +#define PID_DMI 0x2F +#define PID_IOM 0x80 +#define PID_XHCI 0x09 + +/* + * Systemagent + */ +#define SAFBAR 0x68 +#define CRAB_ABORT_BASE_ADDR 0xFEB00000 +#define CRAB_ABORT_SIZE (1 * MiB) +#endif /* _SOC_LUNARLAKE_PLATFORM_SOC_DEFS_H_ */