Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73744 )
Change subject: cpu/qemu-x86/cache_as_ram_bootblock: drop duplicated post code ......................................................................
cpu/qemu-x86/cache_as_ram_bootblock: drop duplicated post code
Before the bootblock stage starts setting up the CAR mode, it sends `POST_BOOTBLOCK_CAR` POST code. However, before the definition for `POST_BOOTBLOCK_CAR` was introduced in the commit 0d34a50a360228138ade623e799b03eaba83b0a5 , the value `0x20` was used. At that point, `0x20` means "entry into CAR mode" and `0x21` means "the cache memory region is cleared". Right now we are sending the same POST code twice, which makes no sense.
So we can do the following (todo: drop me after we decided which one is more appropriate):
1) Drop it (current patchset does exactly that) 2) Introduce POST code similar to POST_SOC_CLEARING_CAR and use it before the cache memory region is cleared.
Change-Id: I5d9014c788abdf5a4338c9e199138d1e514450b3 Signed-off-by: Alexander Goncharov chat@joursoir.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/73744 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Elyes Haouas ehaouas@noos.fr Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com --- M src/cpu/qemu-x86/cache_as_ram_bootblock.S 1 file changed, 29 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 617da53..b414ca1 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -29,8 +29,6 @@ xorl %eax, %eax rep stosl
- post_code(0x21) - #if defined(__x86_64__) /* * Copy page tables to final location in DRAM. This prevents some strange