Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34991 )
Change subject: arch/x86: Include stack_top region into postcar_frame ......................................................................
Patch Set 1:
(1 comment)
Patch Set 1:
Patch Set 1:
(1 comment)
I'm not sure we want to go down this route because of how painful all the various corner cases are when wanting WB cache type for increasing loading speed ramstage. microarchitecture details are making consistency hard.
no, as we discussed, WB might have hard to track. this is just to conclude the WB effort with intermediate caching. but i believe this patch should exist in upstream as we were keeping data here and not signaling the same into system while loading postcar. Not sure if APL implementation also requires that ?
coherency definitely wasn't complete, but much of that was handled with the assumption the writes were coherent (even if slow by writing to UC memory).
https://review.coreboot.org/c/coreboot/+/34991/1/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34991/1/src/arch/x86/postcar_loader... PS1, Line 69:
do you mean pcf->stack and pcf->stack_top should point to same address ?
See line 32 above. pcf->stack gets manipulated as things are pushed on it. pcf->stack_top - pcf->stack is the amount of data pushed on to the stack.