[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 )

Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
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Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 
PS3, Line 20: 
            : Also the COS mask selection is mapped to bit 32:33 of MSR
            : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before
            : MSR write instead of eax(mas 31:0). This implementation corrects that
            : as well.
> for CNL, SKL and KBL i could check the mask selection is mapped to LSB. […]

Ah ok, I think my confusion was the layout of the register being different between SoCs. Also I can't seem to find it documented in #575681 (not listed in the MSR chapter 12)

https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block/... 
PS3, Line 394: 	mov	%ebx, %ecx
maybe comment %ecx is now way size? took me some tracing back to find it