Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68077 )
(
24 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/google/chromec: Expand EC share memory for DTTS ......................................................................
ec/google/chromec: Expand EC share memory for DTTS
DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status.
BUG=b:232946420 TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng ericky_cheng@compal.corp-partner.google.com Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077 Reviewed-by: Tim Van Patten timvp@google.com Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 23 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 0914fdd..3200902 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -56,6 +56,7 @@ CHGL, 8, // Charger Current Limit TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number + STTB, 1, // Switch thermal table by body detection status // DFUD must be 0 for the other 31 values to be valid Offset (0x0a), DFUD, 1, // Device Features Undefined