[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID...

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37461 )

Change subject: arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0
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arch/riscv: Fixed exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0

Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/trap_util.S
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/1

diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 8aba48b..8c1f6cc 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -118,6 +118,7 @@
   # someday this gets fixed.
   //csrr sp, mhartid
   csrr sp, 0xf14
+  addi sp, sp, -CONFIG_RISCV_WORKING_HARTID
 .Lsmp_hang:
   bnez sp, .Lsmp_hang