[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Fix TSEG size computation

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30932 )

Change subject: soc/intel/fsp_broadwell_de: Fix TSEG size computation
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Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/#/c/30932/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/30932/1//COMMIT_MSG@12 
PS1, Line 12: Add one MiB to the register value to make TSEG 8MiB instead of 7MiB.
            : Fixes a crash related to SMRR not matching the TSEG region.
> this simply looks like a wrong size was programmed for TSEG size.

ehm nvm...