[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons, Annie Chen, Arthur Heymans, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Naresh Solanki, Nico Huber, Nill Ge, Shuo Liu, TangYiwei, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email )

Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups
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Patch Set 18:

(1 comment)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/79878/comment/13a26723_833e06e8 :
PS15, Line 276:
> Personally I think the current utils are clear to use. […]

The `socket` field is just used in ACPI code generation to make assumptions about the devices that share the same socket. It could be dropped if sorting algorithms are used and proper checks are implemented everywhere.
I'll add that on the TODO list.