Attention is currently required from: Patrick Rudolph. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60668 )
Change subject: sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ......................................................................
sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual(a, b)` with `a == b`.
Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl 2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60668/1
diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 2e86157..6da51c4 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -90,15 +90,15 @@ { If (HPTE) { CreateDWordField(BUF0, _SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { + If (HPAS == 1) { HPT0 = CONFIG_HPET_ADDRESS + 0x1000 }
- If (Lequal(HPAS, 2)) { + If (HPAS == 2) { HPT0 = CONFIG_HPET_ADDRESS + 0x2000 }
- If (Lequal(HPAS, 3)) { + If (HPAS == 3) { HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 5a80ab0..51c3c48 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -247,13 +247,13 @@ * Arg3 - A Buffer containing a list of DWORD capabilities */ /* Check for XHCI */ - If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) + If (Arg0 == ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71")) { Return (^XHC.POSC(Arg2, Arg3)) }
/* Check for PCIe */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3)