[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled

[Angel Pons (Code Review)]

Hello Nico Huber, Tristan Corrick, Arthur Heymans, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47240

to look at the new patch set (#2).

Change subject: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
......................................................................

sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled

Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and
setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF.
Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2.

However, current code doesn't account for this. The result is that
register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is
OBFF-capable but support is disabled, which makes no sense. Given that
reference code and Broadwell both disable OBFF, disable it here too.

Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47240/2