Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, SH Kim.
SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81033?usp=email )
Change subject: mb/google/brya/var/xol: Add VGPIO configurations for CPU PCIe RP ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/81033/comment/c658aa85_113d75ec : PS1, Line 197: /*Add virtual GPIOs for CPU PCIe RP*/
I just copied this GPIO group from https://review.coreboot.org/c/coreboot/+/57875. […]
@Subrata, Do you still think we need to remove this line?
https://review.coreboot.org/c/coreboot/+/81033/comment/9b87f824_9cbd7e0e : PS1, Line 198: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
I just copied it from https://review.coreboot.org/c/coreboot/+/57875. […]
Thanks for the giving access for the bug. I believe it's the same issue as the Kano's one.
Just found a table to configurate vGPIOs related to CPU PCIE ports in FSP for the reference. https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/rpl/...