[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Revise SA lockdown sequence

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )

Change subject: soc/intel/broadwell: Revise SA lockdown sequence
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... 
File src/soc/intel/broadwell/finalize.c:

https://review.coreboot.org/c/coreboot/+/46324/6/src/soc/intel/broadwell/fin... 
PS6, Line 29: 	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31),	/* SA PM */
> Reference code doesn't have this lock bit, and the register changed quite a bit since Sandy Bridge. […]

Checked on Asrock B85M Pro4 with coreboot (which explicitly sets bit 31 of this register), and the register value is the same, so bit 31 can't be written.