Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34908 )
Change subject: cpu/intel: Enter romstage without BIST ......................................................................
cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/romstage.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/romstage.c M src/drivers/intel/fsp1_1/car.c M src/include/cpu/intel/romstage.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/google/slippy/variant.h M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 47 files changed, 63 insertions(+), 182 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 43fbe8a..2880145 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -61,7 +61,7 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard;
- mainboard_romstage_entry(bist); + mainboard_romstage_entry();
/* Check the stack. */ for (i = 0; i < num_guards; i++) { diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 819c2e4..4b5a3b0 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -141,7 +141,6 @@ struct pei_data *pei_data; const void *gpio_map; const struct rcba_config_instruction *rcba_config; - unsigned long bist; void (*copy_spd)(struct pei_data *); }; void romstage_common(const struct romstage_params *params); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 544a93f..43f5109 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -33,14 +33,10 @@ int boot_mode; int wake_from_s3;
- if (params->bist == 0) - enable_lapic(); + enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
- /* Halt if there was a built in self test failure */ - report_bist_failure(params->bist); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index b206e6d..67fbe69 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -37,7 +37,7 @@ }
/* This is the romstage entry called from cpu/intel/car/romstage.c */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h index 328f464..ff0a167 100644 --- a/src/include/cpu/intel/romstage.h +++ b/src/include/cpu/intel/romstage.h @@ -3,7 +3,7 @@
#include <arch/cpu.h>
-void mainboard_romstage_entry(unsigned long bist); +void mainboard_romstage_entry(void);
/* fill_postcar_frame() is called after raminit completes and right before * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 2929c0d..c95eeda 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -26,7 +26,7 @@ return smbus_read_byte(device, address); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { static const struct mem_controller memctrl[] = { { diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index e96de6f..ad09c5c 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -22,7 +22,6 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -223,22 +222,18 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
- if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc();
/* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index de73d01..7a2004f 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> @@ -82,7 +81,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -95,7 +94,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3af82f2..91667de 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -39,7 +39,7 @@ RCBA_END_CONFIG, };
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -94,7 +94,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, };
romstage_common(&romstage_params); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 91834cd..a93c0ed 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> @@ -31,11 +30,10 @@ return smbus_read_byte(device, address); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist);
enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 753f640..e77e3dc 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ @@ -32,11 +31,10 @@ return smbus_read_byte(device, address); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist);
enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 88f61f8..b517429 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> @@ -31,11 +30,10 @@ return smbus_read_byte(device, address); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist);
enable_smbus(); sdram_initialize(); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 387cecb..cc5b764 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ @@ -65,11 +64,10 @@ outb(0x67, PM_IO_BASE + 0x37); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - report_bist_failure(bist);
enable_smbus(); enable_pm(); diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 4e17d34..c3275b5 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -24,7 +24,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -173,14 +172,13 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0;
u8 c_bsel = msr_get_fsb();
- if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc();
@@ -189,9 +187,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index a818b74..8af04e3 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> @@ -66,7 +65,7 @@ pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -79,7 +78,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 7d02843..f15a187 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/intel/speedstep.h> -#include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> @@ -162,7 +161,7 @@ pci_write_config32(LPC_DEV, 0x84, 0x000295); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -176,7 +175,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index ec4541f..16c3b47 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -17,7 +17,6 @@ */
#include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_ops.h> #include <northbridge/intel/x4x/iomap.h> @@ -81,7 +80,7 @@ pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 #if CONFIG(BOARD_FOXCONN_G41S_K) @@ -101,7 +100,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index d14b1c8..2740aaa 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -232,12 +231,11 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0;
- if (bist == 0) - enable_lapic(); + enable_lapic();
#if 0 /* Force PCIRST# */ @@ -252,9 +250,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index bdb0a38..7a2b384 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -21,7 +21,6 @@ #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -135,12 +134,10 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -153,9 +150,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index e20fb7a..c13d4d6 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -22,7 +22,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> @@ -122,7 +121,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -139,7 +138,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..d36971f 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -67,7 +67,7 @@ RCBA_END_CONFIG, };
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -130,7 +130,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, };
/* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index ec5d5ea..3f6d989 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -18,7 +18,7 @@ #include "variant.h"
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { - variant_romstage_entry(bist); + variant_romstage_entry(); } diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h index eec024e..87a228c 100644 --- a/src/mainboard/google/slippy/variant.h +++ b/src/mainboard/google/slippy/variant.h @@ -16,6 +16,6 @@ #ifndef VARIANT_H #define VARIANT_H
-void variant_romstage_entry(unsigned long bist); +void variant_romstage_entry(void);
#endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27..1903588 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -105,7 +105,7 @@ } }
-void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -167,7 +167,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, };
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..3ef8eec 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -102,7 +102,7 @@ spd_file + (spd_index * spd_len), spd_len); }
-void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -162,7 +162,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, };
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 37c7853..71eafc2 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -119,7 +119,7 @@ } }
-void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -179,7 +179,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, };
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 731b357..7fcf085 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -106,7 +106,7 @@ } }
-void variant_romstage_entry(unsigned long bist) +void variant_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -166,7 +166,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = copy_spd, };
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index ab8282c..847cc5f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -197,12 +196,11 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0;
- if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc(); early_superio_config_w83627ehg(); @@ -210,9 +208,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index b43110b..3fd9aab 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -63,7 +63,7 @@ RCBA_END_CONFIG, };
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -136,7 +136,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], - .bist = bist, .copy_spd = NULL, };
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 32b9a9f..15acffb 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -19,7 +19,6 @@ #include <cpu/x86/lapic.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -117,12 +116,11 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0, boot_mode = 0;
- if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc(); /* Enable SuperIO PM */ @@ -132,9 +130,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 2d6e916..ec3e2bf 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -19,7 +19,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> @@ -75,7 +74,7 @@ pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -89,7 +88,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index c7ef09d..db89682 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> @@ -68,7 +67,7 @@ pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; u8 boot_path = 0; @@ -81,7 +80,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c940536..0981fe8 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -18,7 +18,6 @@ #include <delay.h> #include <console/console.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -241,12 +240,11 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0;
- if (bist == 0) - enable_lapic(); + enable_lapic();
/* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -259,9 +257,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 2817023..243e161 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -157,14 +156,13 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc();
@@ -188,9 +186,6 @@ /* Setup the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index e410351..bbb73dd 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_ops.h> #include <superio/smsc/smscsuperio/smscsuperio.h> @@ -60,7 +59,7 @@ pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -74,7 +73,6 @@
console_init();
- report_bist_failure(bist); enable_smbus();
x4x_early_init(); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 73f5bcc..067528b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -23,7 +23,6 @@ #include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> #include <timestamp.h> @@ -167,14 +166,12 @@ smbus_block_write(0x69, 0, 5, block); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u32 reg32; int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - - if (bist == 0) - enable_lapic(); + enable_lapic();
nehalem_early_initialization(NEHALEM_MOBILE);
@@ -197,9 +194,6 @@
console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 590e786..2b8a9ba 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -157,13 +156,12 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- if (bist == 0) - enable_lapic(); + enable_lapic();
/* Enable GPIOs */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); @@ -190,9 +188,6 @@ else printk(BIOS_DEBUG, "Dock is not present\n");
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 4c487c0..8946179 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -24,7 +24,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -157,14 +156,13 @@ RCBA32(0x2034) = reg32; }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0; int dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
- if (bist == 0) - enable_lapic(); + enable_lapic();
ich7_enable_lpc();
@@ -188,9 +186,6 @@ /* Setup the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index e2c5133..a4d598f 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -23,7 +23,6 @@ #include <cpu/x86/lapic.h> #include <romstage_handoff.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> #include <timestamp.h> @@ -159,7 +158,7 @@ } #endif
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u32 reg32; int s3resume = 0; @@ -169,8 +168,7 @@ outb(4, 0x61); outb(0, 0x61);
- if (bist == 0) - enable_lapic(); + enable_lapic();
nehalem_early_initialization(NEHALEM_MOBILE);
@@ -196,9 +194,6 @@
console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 02ee004..196f0a5 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -24,7 +24,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -204,12 +203,11 @@ outb(0xf4, 0x88); }
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0;
- if (bist == 0) - enable_lapic(); + enable_lapic();
/* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); @@ -222,9 +220,6 @@ /* Set up the console */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); system_reset(); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index e43302a..228bcb5 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -38,7 +38,7 @@ RCBA_END_CONFIG, };
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -92,7 +92,6 @@ .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, - .bist = bist, };
romstage_common(&romstage_params); diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 38f2d5f..7c16761 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <northbridge/intel/gm45/gm45.h> #include <southbridge/intel/i82801ix/i82801ix.h> @@ -47,7 +46,7 @@ /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { sysinfo_t sysinfo; int s3resume = 0; @@ -57,8 +56,7 @@ /* basic northbridge setup, including MMCONF BAR */ gm45_early_init();
- if (bist == 0) - enable_lapic(); + enable_lapic();
/* First, run everything needed for console output. */ i82801ix_early_init(); @@ -69,7 +67,6 @@ mb_setup_superio();
console_init(); - report_bist_failure(bist);
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 8d7de45..e184f78 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -27,7 +27,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> #include <cpu/intel/romstage.h> -#include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include "raminit.h" #include "pineview.h" @@ -48,14 +47,13 @@
#define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0)
-void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u8 spd_addrmap[4] = {}; int boot_path, cbmem_was_initted; int s3resume = 0;
- if (bist == 0) - enable_lapic(); + enable_lapic();
/* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); @@ -63,9 +61,6 @@
setup_pch_gpios(&mainboard_gpio_map);
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - enable_smbus();
/* Perform some early chipset initialization required diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 2cef5f2..bfcf79d 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -22,7 +22,6 @@ #include <cpu/x86/lapic.h> #include <timestamp.h> #include "sandybridge.h" -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <device/pci_def.h> #include <device/device.h> @@ -44,15 +43,14 @@ /* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { int s3resume = 0;
if (MCHBAR16(SSKPD) == 0xCAFE) system_reset();
- if (bist == 0) - enable_lapic(); + enable_lapic();
/* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); @@ -68,9 +66,6 @@ /* Initialize console device(s) */ console_init();
- /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index fffce7e..3dc24f0 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -25,7 +25,6 @@ #include <soc/mrc_wrapper.h>
struct romstage_params { - unsigned long bist; struct mrc_params *mrc_params; };
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 6bf8aac..cf6a856 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -115,10 +115,9 @@ }
/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +static void romstage_main(uint64_t tsc) { struct romstage_params rp = { - .bist = bist, .mrc_params = NULL, };
@@ -159,7 +158,7 @@ */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - romstage_main(base_timestamp, bist); + romstage_main(base_timestamp); }
static struct chipset_power_state power_state; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 5ae39dd..e7b8ae0 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -49,7 +49,7 @@ }
/* Entry from cpu/intel/car/romstage.c. */ -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { struct romstage_params rp = { 0 };