[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: support for mem64 non-prefetchable BAR assignment

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40500 )

Change subject: soc/intel/xeon_sp: support for mem64 non-prefetchable BAR assignment
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Patch Set 1:

This fixes a bug in xeon-sp PCIe code. Currently the code is only effective for SKX-SP. After this patch is merged, we will move PCIe code to soc/intel/xeon_sp directory out from soc/intel/xeon_sp/skx directory, because the same logic works for CPX-SP. In future, we will work with the community to update coreboot PCIe common code (src/device/device.c) to support xeon-sp split IIO stack design.