[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers

[Felix Held (Code Review)]

Hello Patrick Rudolph, HAOUAS Elyes, Arthur Heymans, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37969

to look at the new patch set (#2).

Change subject: nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers
......................................................................

nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers

This patch didn't change the resulting binary for an X230 when using
TIMELESS_BUILD=1

Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5
Signed-off-by: Felix Held 
---
M src/northbridge/intel/sandybridge/finalize.c
M src/northbridge/intel/sandybridge/memmap.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/sandybridge.h
4 files changed, 47 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/37969/2