build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48502 )
Change subject: [WIP]soc/intel/xeon_sp: Allow experimental long mode support ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... File src/soc/intel/xeon_sp/nb_acpi.c:
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 332: /* ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 333: /* assert(ptr != NULL); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 334: /* memset(ptr, 0, size); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 338: /* printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 339: /* "End Address (limit): 0x%x\n", */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 340: /* 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); */ please, no space before tabs
https://review.coreboot.org/c/coreboot/+/48502/1/src/soc/intel/xeon_sp/nb_ac... PS1, Line 342: /* (uint32_t) ((uint32_t) ptr + size - 1)); */ please, no space before tabs