[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Set BootMode based on previous sleep state

[Ravishankar Sarawadi]

Ravishankar Sarawadi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14550

-gerrit

commit 6b4f19c4e5e72c3865158021122ea7e344256797
Author: Ravi Sarawadi 
Date:   Wed Apr 27 15:20:14 2016 -0700

soc/apollolake: Set BootMode based on previous sleep state

- fill_power_state makes a copy of the current snapshot of power
      management
      registers in CAR variable "power_state" for use in ramstage
    - migrate_power_state adds CAR variable "power_state" to
      CBMEM (CBMEM_ID_POWER_STATE)
    - s3_resume state is updated in romstage_handoff block

Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf
    Signed-off-by: Hannah Williams 
    Signed-off-by: Ravi Sarawadi 
---
 src/soc/intel/apollolake/romstage.c | 61 ++++++++++++++++++++++++++++++++++---
 1 file changed, 56 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 9dcb26a..4d274ed 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -17,6 +17,7 @@
  */

#include <assert.h>
+#include <reset.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/symbols.h>
@@ -35,9 +36,15 @@
 #include <soc/northbridge.h>
 #include <soc/romstage.h>
 #include <soc/uart.h>
+#include <soc/pm.h>
+#include <fsp/api.h>
+#include <romstage_handoff.h>
+#include <arch/early_variables.h>

#define FIT_POINTER				(0x100000000ULL - 0x40)

+static struct chipset_power_state power_state CAR_GLOBAL;
+
 /*
  * Enables several BARs and devices which are needed for memory init
  * - MCH_BASE_ADDR is needed in order to talk to the memory controller
@@ -77,6 +84,22 @@ static void disable_watchdog(void)
    outl(reg, ACPI_PMIO_BASE + 0x68);
 }

+static void migrate_power_state(int is_recovery)
+{
+        struct chipset_power_state *ps_cbmem;
+        struct chipset_power_state *ps_car;
+
+        ps_car = car_get_var_ptr(&power_state);
+        ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
+
+        if (ps_cbmem == NULL) {
+                printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n");
+                return;
+        }
+        memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
+}
+ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state);
+
 asmlinkage void car_stage_entry(void)
 {
    void *hob_list_ptr, *mrc_data;
@@ -84,6 +107,9 @@ asmlinkage void car_stage_entry(void)
    struct postcar_frame pcf;
    size_t  mrc_data_size;
    uintptr_t top_of_ram;
+	int prev_sleep_state;
+	struct romstage_handoff *handoff;
+	struct chipset_power_state *ps = car_get_var_ptr(&power_state);

printk(BIOS_DEBUG, "Starting romstage...\n");

@@ -91,6 +117,8 @@ asmlinkage void car_stage_entry(void)

disable_watchdog();

+	prev_sleep_state = fill_power_state(ps);
+
    /* Make sure the blob does not override our data in CAR */
    range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end,
    		(uintptr_t)_car_region_end, 0);
@@ -102,8 +130,17 @@ asmlinkage void car_stage_entry(void)
    fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);

/* initialize cbmem by adding FSP reserved memory first thing */
-	cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
-					range_entry_size(&fsp_mem));
+	if (prev_sleep_state != SLEEP_STATE_S3) {
+		cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+			range_entry_size(&fsp_mem));
+	} else if(cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+		range_entry_size(&fsp_mem))) {
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+		/* Failed S3 resume, reset to come up cleanly */
+		hard_reset();
+#endif
+	}

/* make sure FSP memory is reserved in cbmem */
    if (range_entry_base(&fsp_mem) !=
@@ -114,7 +151,8 @@ asmlinkage void car_stage_entry(void)
    fsp_save_hob_list(hob_list_ptr);

/* Save MRC Data to CBMEM */
-	if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS))
+	if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) &&
+	    (prev_sleep_state != SLEEP_STATE_S3))
    {
    	/* TODO: treat MRC data as const */
    	mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size);
@@ -122,6 +160,13 @@ asmlinkage void car_stage_entry(void)
    		printk(BIOS_ERR, "Failed to stash MRC data\n");
    }

+	/* Create romstage handof information */
+	handoff = romstage_handoff_find_or_add();
+	if (handoff != NULL)
+		handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3);
+	else
+		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+
    if (postcar_frame_init(&pcf, 1*KiB))
    	die("Unable to initialize postcar frame.\n");

@@ -157,6 +202,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
 {
    const struct mrc_saved_data *mrc_cache;
    struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
+	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+	int prev_sleep_state = chipset_prev_sleep_state(ps);

fill_console_params(mupd);
    mainboard_memory_init_params(mupd);
@@ -185,8 +232,12 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
    	if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) {
    		/* MRC cache found */
    		arch_upd->NvsBufferPtr = (void *)mrc_cache->data;
-			arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
-			printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size);
+			arch_upd->Bootmode =
+				prev_sleep_state == SLEEP_STATE_S3 ?
+				FSP_BOOT_ON_S3_RESUME:
+				FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
+			printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n",
+						mrc_cache->size, arch_upd->Bootmode);
    	} else
    		printk(BIOS_DEBUG, "MRC cache was not found\n");
    }