[coreboot-gerrit] [S] Change in coreboot[master]: soc/mediatek/mt8188: enable mfgpll properly and fix SPMI muxes

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yidi Lin.

Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/67355

to look at the new patch set (#2).

Change subject: soc/mediatek/mt8188: enable mfgpll properly and fix SPMI muxes
......................................................................

soc/mediatek/mt8188: enable mfgpll properly and fix SPMI muxes

Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.

- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
  it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
  SPMI kernel driver.

TEST=GPU bringup correctly.
BUG=b:233720142

Signed-off-by: Johnson Wang 
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
---
M src/soc/mediatek/mt8188/pll.c
1 file changed, 24 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/67355/2