[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Support SSPM

[Yidi Lin (Code Review)]

Hello Erin Lo,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/47346

to review the following change.

Change subject: soc/mediatek/mt8192: Support SSPM
......................................................................

soc/mediatek/mt8192: Support SSPM

SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.

Signed-off-by: Erin Lo 
Change-Id: Ie174e8c4f4fc2055b731a3a5ee8d5b49df8af9ac
---
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/sspm.h
A src/soc/mediatek/mt8192/sspm.c
4 files changed, 46 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47346/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index f348a20..22674ca 100755
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -49,6 +49,7 @@
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
+ramstage-y += sspm.c
 ramstage-y += devapc.c
 ramstage-y += ufs.c
 ramstage-y += mcupm.c
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 43a1bdc..b031b16 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -34,6 +34,8 @@
    EMI_BASE		= IO_PHYS + 0x00219000,
    EMI_MPU_BASE		= IO_PHYS + 0x00226000,
    DRAMC_CHA_AO_BASE	= IO_PHYS + 0x00230000,
+	SSPM_SRAM_BASE		= IO_PHYS + 0x00400000,
+	SSPM_CFG_BASE		= IO_PHYS + 0x00440000,
    AUXADC_BASE		= IO_PHYS + 0x01001000,
    DPM_PM_SRAM_BASE	= IO_PHYS + 0x00900000,
    DPM_DM_SRAM_BASE	= IO_PHYS + 0x00920000,
diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h
new file mode 100644
index 0000000..5749fa4
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/sspm.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_SSPM_H
+#define SOC_MEDIATEK_MT8192_SSPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8192_sspm_regs {
+	u32 sw_rstn;
+};
+static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE;
+void sspm_init(void);
+#endif  /* SOC_MEDIATEK_MT8192_SSPM_H */
diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c
new file mode 100644
index 0000000..7f66535
--- /dev/null
+++ b/src/soc/mediatek/mt8192/sspm.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/barrier.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/sspm.h>
+#include <string.h>
+
+#define BUF_SIZE (64 * KiB)
+static uint8_t sspm_bin[BUF_SIZE] __aligned(8);
+
+void sspm_init(void)
+{
+	const char *file_name = "sspm.bin";
+	size_t fw_size = cbfs_boot_load_file(file_name,
+					     sspm_bin,
+					     sizeof(sspm_bin),
+					     CBFS_TYPE_RAW);
+
+	if (fw_size == 0)
+		die("SSPM file :sspm.bin not found.");
+
+	memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size);
+	/* Memory barrier to ensure that all fw code is loaded
+	   before we release the reset pin. */
+	mb();
+	write32(&mt8192_sspm->sw_rstn, 0x1);
+}