Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35383 )
Change subject: drivers/intel/fsp2_0: Allow platform to increase mem overhead ......................................................................
drivers/intel/fsp2_0: Allow platform to increase mem overhead
Add a call and a weak function for an additional amount of DRAM to be considered overhead by the SOC.
This change provides a convenient solution for reserving additional memory, e.g. for AMD TSEG, without requiring explicit passing of additional values to FSP via UPD.
TEST=Implement in Picasso and verify FSP recognizes additional TOLUM requirements.
Change-Id: Ia291273b9b7fda0e34be7879473eabd7b53b47b4 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35383/1
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b905b69..2c3a566 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -58,6 +58,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
+/* Allow the platform to increase BootLoaderTolumSize */ +size_t platform_mem_overhead_size(void); + /* * The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION * is employed allowing the mainboard and SoC to supply their own version diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1386d2c..349a188 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -41,6 +41,8 @@ CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "for TPM MRC hash functionality, vboot must start in bootblock");
+__weak size_t platform_mem_overhead_size(void) { return 0; } + static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -289,8 +291,11 @@
arch_upd = &fspm_upd.FspmArchUpd;
- /* Reserve enough memory under TOLUD to save CBMEM header */ + /* Reserve enough memory under TOLUD to save CBMEM header and any + * additional requirements of the platform implementation. + */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); + arch_upd->BootLoaderTolumSize += platform_mem_overhead_size();
/* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,