[coreboot-gerrit] Change in coreboot[master]: sb/intel/common/spi: Add Baytrail/Braswell support

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36342 )

Change subject: sb/intel/common/spi: Add Baytrail/Braswell support
......................................................................

sb/intel/common/spi: Add Baytrail/Braswell support

Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/spi.h
2 files changed, 57 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/1

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 73181cf..fd53217 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -33,6 +33,10 @@

#include "spi.h"

+#if (!ICH7_SPI && !ICH9_SPI && !BYT_BSW_SPI)
+#error "Unsupported SPI controller!
+#endif
+
 #define HSFC_FCYCLE_OFF		1	/* 1-2: FLASH Cycle */
 #define HSFC_FCYCLE		(0x3 << HSFC_FCYCLE_OFF)
 #define HSFC_FDBC_OFF		8	/* 8-13: Flash Data Byte Count */
@@ -271,6 +275,30 @@
 #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu)
 #endif

+static void *get_spi_bar(void)
+{
+	uint32_t rcba; /* Root Complex Register Block */
+	uint32_t sbase;
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev = PCI_DEV(0, 31, 0);
+#else
+	struct device *dev = pcidev_on_root(31, 0);
+#endif
+	if (ICH7_SPI) {
+		rcba = pci_read_config32(dev, 0xf0);
+		return (void *)((rcba & 0xffffc000) + 0x3020);
+	}
+	if (BYT_BSW_SPI) {
+		sbase = pci_read_config32(dev, 0x52);
+		sbase &= ~0x1ff;
+		return (void *)sbase;
+	}
+	if (ICH9_SPI) {
+		rcba = pci_read_config32(dev, 0xf0);
+		return (void *)((rcba & 0xffffc000) + 0x3800);
+	}
+}
+
 void spi_init(void)
 {
    struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
@@ -281,17 +309,8 @@
    struct ich7_spi_regs *ich7_spi;
    uint16_t hsfs;

-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev = PCI_DEV(0, 31, 0);
-#else
-	struct device *dev = pcidev_on_root(31, 0);
-#endif
-
-	rcba = pci_read_config32(dev, 0xf0);
-	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
-	rcrb = (uint8_t *)(rcba & 0xffffc000);
-	if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
-		ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
+	if (ICH7_SPI) {
+		ich7_spi = get_spi_bar();
    	cntlr->ich7_spi = ich7_spi;
    	cntlr->opmenu = ich7_spi->opmenu;
    	cntlr->menubytes = sizeof(ich7_spi->opmenu);
@@ -306,7 +325,7 @@
    	cntlr->fpr = &ich7_spi->pbr[0];
    	cntlr->fpr_max = 3;
    } else {
-		ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
+		ich9_spi = get_spi_bar();
    	cntlr->ich9_spi = ich9_spi;
    	hsfs = readw_(&ich9_spi->hsfs);
    	cntlr->hsfs = hsfs;
@@ -333,11 +352,20 @@

ich_set_bbar(0);

-	/* Disable the BIOS write protect so write commands are allowed. */
-	bios_cntl = pci_read_config8(dev, 0xdc);
-	/* Deassert SMM BIOS Write Protect Disable. */
-	bios_cntl &= ~(1 << 5);
-	pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
+	if (BYT_BSW_SPI) {
+		/* Disable the BIOS write protect so write commands are allowed. */
+		bios_cntl = readl_(ich9_spi + 0xfc);
+		bios_cntl |= 1;
+		writel_(bios_cntl, ich9_spi + 0xfc);
+	}
+
+	if (ICH7_SPI || ICH9_SPI) {
+		/* Disable the BIOS write protect so write commands are allowed. */
+		bios_cntl = pci_read_config8(dev, 0xdc);
+		/* Deassert SMM BIOS Write Protect Disable. */
+		bios_cntl &= ~(1 << 5);
+		pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
+	}
 }

static int spi_locked(void)
diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h
index 3b8410c..84e183e 100644
--- a/src/southbridge/intel/common/spi.h
+++ b/src/southbridge/intel/common/spi.h
@@ -32,6 +32,18 @@
    struct intel_spi_op ops[8];
 };

+#define ICH7_SPI CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
+#define ICH9_SPI (CONFIG(SOUTHBRIDGE_INTEL_I82801IX) ||		\
+		  CONFIG(SOUTHBRIDGE_INTEL_I82801JX) ||		\
+		  CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK) ||		\
+		  CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) ||		\
+		  CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) ||	\
+		  CONFIG(SOC_INTEL_BROADWELL) ||		\
+		  CONFIG(SOC_INTEL_BROADWELL_DE))
+#define BYT_BSW_SPI (CONFIG(SOC_INTEL_BAYTRAIL) ||	\
+		     CONFIG(SOC_INTEL_FSP_BAYTRAIL) ||	\
+		     CONFIG(SOC_INTEL_BRASWELL))
+
 void spi_finalize_ops(void);
 void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config);