Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39121 )
Change subject: mb/google/dedede: configure ESPI IO decode range for chrome EC ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
(1 comment)
Patch Set 2:
(1 comment)
Patch Set 2:
LGTM, but just a thought, do we want to move the LPC generic IO decode ranges to our EC driver? Then we don't have to keep adding it to every mainboard's devicetree.
This I/O decode range configuration seems to be Intel SoC specific - not the range itself, but the register value. So moving to the EC driver may be tricky and might require SoC knowledge in there.
Actually, these are the I/O windows that Chrome EC uses -- 0x800, 0x900, 0x200. The way they get mapped to LPC I/O regs is specific to Intel, but I think we can do some work to avoid having to duplicate this across mainboards. I believe this was done differently on APL/GLK, but it still required mainboard to provide a function to do the work.
A possible approach is to let the EC driver return the I/O range along with the size info (in dwords or bytes). SoCs use the range information to map to the LPC I/O range registers. That way we can avoid duplicating the configuration in the mainboard.
For now this can go in, while we look into all the mainboards to do clean-up the redundancy. I will take that as an action item on me.