[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: TEST Enable TME from devicetree

[Ronak Kanabar (Code Review)]

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61546 )

Change subject: mb/intel/adlrvp: TEST Enable TME from devicetree
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mb/intel/adlrvp: TEST Enable TME from devicetree

This patch is needed when following patch is used for test.
https://review.coreboot.org/c/coreboot/+/61492

Change-Id: If656b054f4913779da927ee4df83d4f6fbcc9b8d
Signed-off-by: Ronak Kanabar 
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_n.cb
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/61546/1

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 9bd99b1..0d357dc 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -16,6 +16,9 @@
    # Sagv Configuration
    register "SaGv" = "SaGv_Enabled"

+	#Enable Total Memory Encryption
+	register "enable_tme" = "true"
+
    register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
    register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
    register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index f013596..79cb57c 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -16,6 +16,9 @@
    # Sagv Configuration
    register "SaGv" = "SaGv_Enabled"

+	#Enable Total Memory Encryption
+	register "enable_tme" = "true"
+
    register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
    register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
    register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3