[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/i2c: do not init I2C4

[Felix Held (Code Review)]

Hello Martin Roth, Magf -,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40248

to review the following change.

Change subject: soc/amd/picasso/i2c: do not init I2C4
......................................................................

soc/amd/picasso/i2c: do not init I2C4

I2C4 is slave device only, so do not init it as I2C host controller.

BUG=b:150916992
BRANCH=none
TEST=build and test dalboz, AP mux can be accessed successfully.

Change-Id: I6a3ddecd293f550a4df5e667094c69f5c115e29c
Signed-off-by: Paul Ma 
Reviewed-on: https://chromium-review.googlesource.com/2094855
Tested-by: Martin Roth 
Reviewed-by: Martin Roth 
---
M src/soc/amd/picasso/i2c.c
M src/soc/amd/picasso/include/soc/iomap.h
2 files changed, 5 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/40248/1

diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c
index 2bd3116..a3e34c8 100644
--- a/src/soc/amd/picasso/i2c.c
+++ b/src/soc/amd/picasso/i2c.c
@@ -18,12 +18,15 @@
 /* Global to provide access to chip.c */
 const char *i2c_acpi_name(const struct device *dev);

+/*
+ * I2C4 is slave device only, do not list it here,
+ * otherwise this slave device will not be able to work.
+ */
 static const uintptr_t i2c_bus_address[] = {
    APU_I2C0_BASE,
    APU_I2C1_BASE,
    APU_I2C2_BASE,
    APU_I2C3_BASE,
-	APU_I2C4_BASE, /* slave device only */
 };

_Static_assert(ARRAY_SIZE(i2c_bus_address) == I2C_DEVICE_COUNT,
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 3f539a2..edd9ff1 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -26,7 +26,7 @@
 #define APU_I2C4_BASE			0xfedc6000
 #define   I2C_BASE_ADDRESS		APU_I2C0_BASE
 #define   I2C_DEVICE_SIZE		0x00001000
-#define   I2C_DEVICE_COUNT		5
+#define   I2C_DEVICE_COUNT		4

#define APU_DMAC0_BASE			0xfedc7000
 #define APU_DMAC1_BASE			0xfedc8000