Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.
Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74788 )
Change subject: vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP ......................................................................
vc/amd/fsp/mendocino/FspmUpd: Update Update UPD structure for MDN-FSP
Update UPD structure to align with MDN-FSP.
BUG=b:271704149 BRANCH=none Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 --- M src/vendorcode/amd/fsp/mendocino/FspmUpd.h 1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74788/1
diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index b3d6dc3..e2622dd 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -102,7 +102,8 @@ /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; - /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EB**/ uint8_t edp_panel_t9_ms; + /** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG;