Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29172
Change subject: soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIG ......................................................................
soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIG
SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the first definition are unused. Remove first definition and its associated bits and shifts.
BUG=b:117818430 TEST=Build grunt.
Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 1 insertion(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29172/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9f940c0..3d0df68 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -351,15 +351,10 @@ #define SPI_FIFO 0x80 #define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
-#define SPI100_SPEED_CONFIG 0x22 -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) -#define SPI_NORM_SPEED_SH 12 -#define SPI_FAST_SPEED_SH 8 - #define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0)
+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ #define SPI100_SPEED_CONFIG 0x22 #define SPI_SPEED_66M (0x0) #define SPI_SPEED_33M ( BIT(0))