[coreboot-gerrit] Change in coreboot[master]: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout

[Uwe Poeche (Code Review)]

Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34173 )

Change subject: southbridge/intel/common/spi.c: Increase SPI-flash erase timeout
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Patch Set 3:

(4 comments)

https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@1 
PS1, Line 1: Parent:     cb587a25 (drivers/intel: Move FSP stage_cache implementation into common block)
> This is not just mc_bdx1 related but hits the overall common SPI-driver. […]

Done

https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@7 
PS1, Line 7: i
> Please start with a upper case letter

Done

https://review.coreboot.org/c/coreboot/+/34173/1//COMMIT_MSG@14 
PS1, Line 14:  operation if the
> that is more than 80 columns

Done

https://review.coreboot.org/c/coreboot/+/34173/1/src/southbridge/intel/commo... 
File src/southbridge/intel/common/spi.c:

https://review.coreboot.org/c/coreboot/+/34173/1/src/southbridge/intel/commo... 
PS1, Line 730: 	uint32_t timeout = 1000 * 200;
> The function signature takes an unsigned integer. […]

Done