Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/20532
Change subject: soc/intel/skylake: Log wakes due to PCIE root port ......................................................................
soc/intel/skylake: Log wakes due to PCIE root port
When wake happens due to PME on PCIE root port, then update the same in elog.
BUG=b:36992859 TEST=Build for Soraka, Verify resume due to PME on root port is updated in elog.
Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 Signed-off-by: Naresh G Solanki naresh.solanki@intel.com --- M src/soc/intel/skylake/elog.c 1 file changed, 41 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/20532/1
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index fde8be2..69bc25e 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -200,20 +200,6 @@ static const struct pme_status_info pme_status_info[] = { { PCH_DEVFN_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, { PCH_DEVFN_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, - { PCH_DEVFN_EMMC, 0x84, ELOG_WAKE_SOURCE_PME_EMMC }, - { PCH_DEVFN_SDCARD, 0x84, ELOG_WAKE_SOURCE_PME_SDCARD }, - { PCH_DEVFN_PCIE1, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE1 }, - { PCH_DEVFN_PCIE2, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE2 }, - { PCH_DEVFN_PCIE3, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE3 }, - { PCH_DEVFN_PCIE4, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE4 }, - { PCH_DEVFN_PCIE5, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE5 }, - { PCH_DEVFN_PCIE6, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE6 }, - { PCH_DEVFN_PCIE7, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE7 }, - { PCH_DEVFN_PCIE8, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE8 }, - { PCH_DEVFN_PCIE9, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE9 }, - { PCH_DEVFN_PCIE10, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE10 }, - { PCH_DEVFN_PCIE11, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE11 }, - { PCH_DEVFN_PCIE12, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE12 }, { PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, { PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, { PCH_DEVFN_CSE_2, 0x54, ELOG_WAKE_SOURCE_PME_CSE2 }, @@ -228,7 +214,7 @@ if (!dev) continue;
- val = pci_read_config16(dev, pme_status_info[i].reg_offset); + val = pci_read_config32(dev, pme_status_info[i].reg_offset);
if ((val == 0xFFFF) || !(val & PME_STS_BIT)) continue; @@ -239,6 +225,43 @@
if (!dev_found) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + +#define RP_PME_STS_BIT (1 << 16) +static void pch_log_rp_wake_source(void) +{ + size_t i; + device_t dev; + uint32_t val; + + static const struct pme_status_info pme_status_info[] = { + { PCH_DEVFN_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + dev = dev_find_slot(0, pme_status_info[i].devfn); + + if (!dev) + continue; + + val = pci_read_config32(dev, pme_status_info[i].reg_offset); + + if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT)) + continue; + + pch_log_add_elog_event(&pme_status_info[i], dev); + } }
static void pch_log_wake_source(struct chipset_power_state *ps) @@ -263,6 +286,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) pch_log_pme_internal_wake_source();
+ /* PCIE Root Port */ + pch_log_rp_wake_source(); + /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);